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參數(shù)資料
| 型號： | MAX7325ATG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 24TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時(shí)鐘： | 400kHz |
| 電源電壓： | 1.71 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
| 包括： | POR |
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
14
Maxim Integrated
Typically, the master reads one byte from the push-pull
ports of the MAX7325, then issues a STOP condition
(Figure 8). However, the master can read two or more
bytes from the group B ports of the MAX7325, then
issues a STOP condition. In this case, the MAX7325
resamples the port outputs during each acknowledge
and transmits the new data each time.
Writing the MAX7325
A write to either output port groups of the MAX7325
starts with the master transmitting the group’s slave
address with the R/W bit set low. The MAX7325
acknowledges the slave address and samples the
ports during the acknowledge bit. INT goes high (high
impedance if an external pullup resistor is not fitted)
during the slave acknowledge only when it writes to the
open-drain ports. The master can now transmit one or
more bytes of data. The MAX7325 acknowledges these
subsequent bytes of data and updates the correspond-
ing group’s ports with each new byte until the master
issues a STOP condition (Figure 9).
Applications Information
Port Input and I2C Interface Level
Translation from Higher or
Lower Logic Voltages
The MAX7325’s SDA, SCL, AD0, AD2, RST, INT, O8–O15,
and P0–P7 are overvoltage protected to +6V. This
allows the MAX7325 to operate from a lower supply
voltage, such as +3.3V, while the I2C interface and/or
any of the eight I/O ports are driven as inputs from a
higher logic level, such as +5V.
The MAX7325 can operate from a higher supply volt-
age, such as +3V, while the I2C interface and/or some
of the I/O ports P0–P7 are driven from a lower logic
level, such as +2.5V. For V+ < 1.8V, apply a minimum
voltage of 0.8 x V+ to assert a logic-high on any input.
For a V+
≥ 1.8V, apply a voltage of 0.7 x V+ to assert a
logic-high. For example, a MAX7325 operating from a
+5V supply may not recognize a +3.3V nominal logic-
high. One solution for input-level translation is to drive
MAX7325 I/Os from open-drain outputs. Use a pullup
resistor to V+ or a higher supply to ensure a high logic
voltage greater than 0.7 x V+.
Port Output Signal-Level Translation
The open-drain output architecture allows for level trans-
lation to higher or lower voltages than the MAX7325’s
supply. Use an external pullup resistor on any output to
convert the high-impedance logic-high condition to a
positive voltage level. The resistor can be connected to
any voltage up to +6V, and the resistor value chosen to
ensure no more than 20mA is sunk in the logic-low condi-
tion. For interfacing CMOS inputs, a pullup resistor value
of 220k
is a good starting point. Use a lower resistance
to improve noise immunity, in applications where power
consumption is less critical, or where a faster rise time is
needed for a given capacitive load.
Each of the push-pull output ports has protection
diodes to V+ and GND. When a port output is driven to
a voltage higher than V+ or lower than GND, the appro-
priate protection diode clamps the output to a diode
drop above V+ or below GND. When the MAX7325 is
powered down (V+ = 0V), every output port’s protection
SCL
SDA
SLAVE ADDRESS
S0
123
4
5
6
7
8
AA
A
DATA 1
DATA 2
DATA TO INTERRUPT MASK
START CONDITION
R/W ACKNOWLEDGE
FROM SLAVE
tPV
DATA 2 VALID
DATA 1 VALID
INTERNAL WRITE
TO PORT
DATA OUT
FROM PORT
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
tPV
Figure 9. Writing to the MAX7325
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| MAX7326AEG | 功能描述:接口-I/O擴(kuò)展器 I2C Port Expander w/12 P-P Out & 4 In RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
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