1-to-8 I2C Bus Switches/Multiplexers with Bus Lock-Up De" />
參數(shù)資料
型號(hào): MAX7358EUG+T
廠商: Maxim Integrated Products
文件頁數(shù): 19/22頁
文件大?。?/td> 0K
描述: IC MULTIPLEXER 8X1 24TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 多路復(fù)用器
電路: 1 x 8:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
MAX7356/MAX7357/MAX7358
1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3) (continued)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
Note 2: All devices are 100% production tested at TA = +25°C. Specifications are over -40°C to +85°C and are guaranteed by
design.
Note 3: Subscript SW refers to all SC_ and SD_ pins.
Note 4: VSWin = Switch input voltage; ISWout = Current between SD_ and SDA or SC_ and SCL. See Figure 4.
Note 5: VI = VSD_ or VSC_.
Note 6: All timing is measured using 20% and 80% levels, unless otherwise noted.
Note 7: Pass gate propagation delay is calculated from the 20
typical RON and the 15pF load capacitance.
Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(min) of the SCL signed)
to bridge the undefined region of the falling edge of SCL.
SDA
SCL
tBUF
tSU;STO
tSP
tHD;STA
tSU;STA
tF
tHIGH
tHD;DAT
tR
tLOW
tHD;STA
S
P
Sr
P
tSU;DAT
Figure 1. 2-Wire Serial-Interface Timing Diagram
SCL
SDA
RESET
tREC;STA
tWL(rst)
trst
Figure 2.
RST Timing Diagram
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