參數(shù)資料
型號(hào): MAX7425EUA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/14頁(yè)
文件大?。?/td> 0K
描述: IC FILTER LOWPASS 5TH 8UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
濾波器類型: 橢圓,低通開關(guān)電容器
頻率 - 截止或中心: 45kHz
濾波器數(shù): 1
濾波器階數(shù): 5th
電源電壓: 2.7 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
配用: MAXFILTERBRD+-ND - BOARD EVAL MAX7408/7415/418-7425
MAX7418–MAX7425
5th-Order, Lowpass,
Switched-Capacitor Filters
______________________________________________________________________________________
11
Internal Clock
When using the internal oscillator, the capacitance
(COSC) on CLK determines the oscillator frequency:
where
k=87x103 for the
MAX7418/MAX7421/MAX7422/MAX7425
and
k=110X103 for the
MAX7419/MAX7420/MAX7423/ MAX7424.
Since COSC is in the low picofarads, minimize the stray
capacitance at CLK so that it does not affect the inter-
nal oscillator frequency. Varying the rate of the internal
oscillator adjusts the filter’s corner frequency by a
100:1 clock-to-corner frequency ratio. For example, an
internal oscillator frequency of 2.2kHz produces a nom-
inal corner frequency of 2.2MHz.
Input Impedance vs. Clock Frequencies
The MAX7418–MAX7425s’ input impedance is effective-
ly that of a switched-capacitor resistor (see the following
equation), and is inversely proportional to frequency.
The input impedance values determined by the equa-
tion represent the average input impedance, since the
input current is not continuous. As a rule, use a driver
with an output resistance less than 10% of the filter’s
input impedance.
Estimate the input impedance of the filter by using the
following formula:
where fCLK = clock frequency and CIN = 1pF.
Low-Power Shutdown Mode
The MAX7418–MAX7425 have a shutdown mode that is
activated by driving
SHDN low. In shutdown mode, the
filter supply current reduces to 0.2A, and the output of
the filter becomes high impedance. For normal opera-
tion, drive
SHDN high or connect to VDD.
Applications Information
Offset (OS) and Common-Mode (COM)
Input Adjustment
COM sets the common-mode input voltage and is
biased at midsupply with an internal resistor-divider. If
the application does not require offset adjustment, con-
nect OS to COM. For applications in which offset
adjustment is required, apply an external bias voltage
through a resistor-divider network to OS, as shown in
Figure 4. For applications that require DC level shifting,
adjust OS with respect to COM. (Note: Do not leave OS
unconnected.) The output voltage is represented by
these equations:
where (VIN - VCOM) is lowpass filtered by the SCF and
OS is added at the output stage. See the
Electrical
VV
V
typical
OUT
IN
COM
OS
COM
DD
(
)
()
=
+
=
2
Z
1
(f
C )
IN
CLK
IN
=
×
fOSC(kHz)
k
COSC(pF)
=
VDD
VSUPPLY
IN
CLK
GND
INPUT
OUTPUT
50k
OUT
0.1
μF
0.1
μF
0.1
μF
CLOCK
SHDN
COM
OS
MAX7418–
MAX7425
Figure 4. Offset Adjustment Circuit
A
2V/div
C
A: 1kHz INPUT SIGNAL
B: MAX7419 BESSEL FILTER RESPONSE; fC = 5kHz
C: MAX7420 BUTTERWORTH FILTER RESPONSE; fC = 5kHz
B
200
μs/div
Figure 3. Bessel vs. Butterworth Filter Response
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