參數(shù)資料
型號(hào): MAX824M
廠商: Maxim Integrated Products, Inc.
英文描述: 5-Pin Microprocessor Supervisory Circuits(復(fù)位門(mén)限4.38V,5管腳μP監(jiān)控電路,具看門(mén)狗輸入和高有效復(fù)位)
中文描述: 5引腳、微處理器監(jiān)控電路,帶有看門(mén)狗定時(shí)器及手動(dòng)復(fù)位
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 81K
代理商: MAX824M
M
5-Pin Mic roproc essor S upervisory Circ uits
6
_______________________________________________________________________________________
_______________Detailed Desc ription
RES ET Output
A microprocessor’s (μP’s) reset input starts the μP in a
known state. The MAX823/MAX824/MAX825 μP super-
visory circuits assert a reset to prevent code-execution
errors during power-up, power-down, and brownout
conditions.
RESET
is guaranteed to be a logic low for
V
CC
down to 1V. Once V
CC
exceeds the reset thresh-
old, an internal timer keeps
RESET
low for the specified
reset timeout period (t
RP
); after this interval,
RESET
returns high (Figure 2).
If a brownout condition occurs (V
CC
dips below the
reset threshold),
RESET
goes low. Each time
RESET
is
asserted it stays low for the reset timeout period. Any
time V
CC
goes below the reset threshold the internal
timer restarts.
RESET
both sources and sinks current.
RESET on the MAX824/MAX825 is the inverse of
RESET
.
Manual-Reset Input (MAX 823/MAX 825)
Many μP-based products require manual-reset capabili-
ty, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. On the MAX823/
MAX825, a logic low on
MR
asserts reset. Reset remains
asserted while
MR
is low, and for t
RP
(200ms nominal)
after it returns high.
MR
has an internal 52k
pull-up
resistor, so it can be left open if not used. This input can
be driven with CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open momentary
switch from
MR
to GND to create a manual-reset func-
tion; external debounce circuitry is not required. If
MR
is
driven from long cables or the device is used in a noisy
environment, connect a 0.1μF capacitor from
MR
to
GND to provide additional noise immunity.
Watc hdog Input (MAX 823/MAX 824)
In the MAX823/MAX824, the watchdog circuit monitors
the μP’s activity. If the μP does not toggle the watchdog
input (WDI) within t
WD
(1.6sec), reset asserts. The inter-
nal 1.6sec timer is cleared by either a reset pulse or by
toggling WDI, which detects pulses as short as 50ns.
While reset is asserted, the timer remains cleared and
does not count. As soon as reset is released, the timer
starts counting (Figure 3).
Disable the watchdog function by leaving WDI uncon-
nected or by three-stating the driver connected to WDI.
The watchdog input is internally driven low during the
first 7/8 of the watchdog timeout period and high for the
last 1/8 of the watchdog timeout period. When WDI is
left unconnected, this internal driver clears the 1.6sec
timer every 1.4sec. When WDI is three-stated or uncon-
nected, the maximum allowable leakage current is
10μA and the maximum allowable load capacitance is
200pF.
__________Applic ations Information
Watc hdog Input Current
The MAX823/MAX824 WDI inputs are internally driven
through a buffer and series resistor from the watchdog
counter (Figure 1). When WDI is left unconnected, the
watchdog timer is serviced within the watchdog timeout
period by a low-high-low pulse from the counter chain.
For minimum watchdog input current (minimum overall
power consumption), leave WDI low for the majority of
the watchdog timeout period, pulsing it low-high-low
once within the first 7/8 of the watchdog timeout period
to reset the watchdog timer. If WDI is externally driven
high for the majority of the timeout period, up to 160μA
can flow into WDI.
V
CC
1V
1V
t
RD
V
RST
V
RST
t
RD
RESET
GND
RESET
t
RP
t
RP
Figure 2. Reset Timing Diagram
V
CC
t
WD
t
RP
t
RP
t
RST
WDI
RESET*
*RESET ON THE MAX824/MAX825 IS THE INVERSE OF RESET.
Figure 3. MAX823/MAX824 Watchdog Timing Relationship
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