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| 型號(hào)： | MAX8890EGCMLF |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 57K |
| 代理商： | MAX8890EGCMLF |
E
MAX 881R Evaluation K it
2
_______________________________________________________________________________________
Detailed Desc ription
J umper S elec tion
The 2-pin header, J U1, controls pin 5 (
SHDN
Table 1 outlines the shunt positions for J U1.
The
POK
pad allows easy connection to an external
system. This output pulls low when the bias voltage has
reached 92.5% of its set value.
Output V oltage Adjustment
For output voltages other than -2V, install R1 to com-
plete the R1/R2 output voltage divider. R2 is a 100k
,
1% resistor. To maintain accuracy, use a 1% resistor for
R1. Use the following equations to calculate R1:
R1 = -R2 (2 x V
OUT
+ 1)
R1 = -100k
(2 x V
OUT
+ 1)
Capac itor S elec tion
Use capacitors with a low effective series resistance
(ESR), such as ceramic or surface-mount chip tantalum
types.
Output ripple with the supplied components is typically
1mVp-p. For lower output ripple, replace C4 with a
10μF ceramic capacitor such as the Taiyo Yuden
J MK316BJ 106ML or a 10μF tantalum such as the
Sprague 595D106X0010A2.
Table 1. JU1 Shunt Position
SHUNT POSITION
MAX881R FUNCTION
Open
Device enabled, or
apply signal to the
SHDN
pad
Closed
Device disabled
Figure 1. MAX881R EV Kit Schematic
C1+
C1-
NEGOUT
C3
1
μ
F
C1
1
μ
F
C2
1
μ
F
C4
4.7
μ
F
R1
OPEN
R2
100k
1%
R3
1M
R4
1M
POK
SHDN
1
2
3
4
5
10
9
8
7
6
SHDN
JU1
IN
V
IN
2.5V to 5.5V
N.C.
GND
GND
VOUT
VOUT
GND
J1
OUT
FB
MAX881R
U1
POK
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