參數(shù)資料
型號: MAX8893AEWV+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA30
封裝: 3 X 2.50 MM, 0.64 MM HEIGHT, ROHS COMPLIANT, WLP-30
文件頁數(shù): 26/51頁
文件大?。?/td> 4976K
代理商: MAX8893AEWV+
PMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
MAX8893A/MAX8893B/MAX8893C
32 _____________________________________________________________________________________
Slave Address
A bus master initiates communication with a slave
device (MAX8893A/MAX8893B/MAX8893C) by issuing
a START condition followed by the slave address. The
slave address byte consists of 7 address bits (0111110)
and a read/write bit (RW). Its address is 0x7C for write
operations and 0x7D for read operations. After receiv-
ing the proper address, the MAX8893A/MAX8893B/
MAX8893C issue an acknowledge by pulling SDA low
during the ninth clock cycle.
Bit Transfer
Each data bit, from the most significant bit to the least
significant bit, is transferred one by one during each
clock cycle. During data transfer, the SDA signal is
allowed to change only during the low period of the SCL
clock and it must remain stable during the high period of
the SCL clock (Figure 9).
START and STOP Conditions
Both SCL and SDA remain high when the bus is not busy.
The master signals the beginning of a transmission with
a START (S) condition by transitioning SDA from high to
low while SCL is high. When the master has finished com-
municating with the MAX8893A/MAX8893B/MAX8893C,
it issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 10). Both START and STOP
conditions are generated by the bus master.
Figure 9. Bit Transfer
Figure 10. START and STOP Conditions
START
CONDITION
(S)
DATA LINE STABLE
DATA VALID
DATA ALLOWED TO
CHANGE
STOP
CONDITION
(P)
SCL
SDA
SCL
START
CONDITION
STOP
CONDITION
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