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參數(shù)資料
| 型號： | MAX9121 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout |
| 中文描述： | 四路LVDS線接收器，內(nèi)部端接，引腳按信號流向排列 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 231K |
| 代理商： | MAX9121 |
M
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
6
_______________________________________________________________________________________
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS stan-
dard uses a lower voltage swing than other common
communication standards, achieving higher data rates
with reduced power consumption while reducing EMI
emissions and system susceptibility to noise.
The MAX9121/MAX9122 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS out-
put. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally cen-
tered around a +1.2V offset. This offset, coupled with
the receiver
’
s 0 to 2.4V input voltage range, allows an
approximate ±1V shift in the signal (as seen by the
receiver). This allows for a difference in ground refer-
ences of the transmitter and the receiver, the common-
mode effects of coupled noise, or both. The LVDS stan-
dards specify an input voltage range of 0 to +2.4V
referenced to receiver ground.
The MAX9122 has an integrated termination resistor
that is internally connected across each receiver input.
The internal termination saves board space, eases lay-
out, and reduces stub length compared to an external
termination resistor. In other words, the transmission
line is terminated on the IC.
Fail-Safe
The fail-safe feature of the MAX9121/MAX9122 sets an
output high when:
Inputs are open.
Inputs are undriven and shorted.
Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the inputs may switch the receiver
and it may appear to the system that data is being
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 8
IN_-
Inverting Differential Receiver Inputs
2, 3, 6, 7
IN_+
Noninverting Differential Receiver Inputs
9, 16
EN
, EN
Receiver Enable Inputs. When EN = high and
EN
= low or open, the outputs are active. For
other combinations of EN and
EN
, the outputs are disabled and in high impedance.
10, 11, 14, 15
OUT_
LVCMOS/LVTTL Receiver Outputs
12
GND
Ground
13
V
CC
Power-Supply Input. Bypass V
CC
to GND with 0.1μF and 0.001μF ceramic capacitors.
Table 1. Input/Output Function Table
ENABLES
INPUTS
OUTPUT
EN
EN
(IN_+) - (IN_-)
V
ID
≥
+100mV
V
ID
≤
-100mV
Open, undriven short, or undriven
100
parallel termination
Open or undriven short
Don
’
t care
OUT_
H
L
MAX9121
H
L or open
MAX9122
H
All other combinations of ENABLE pins
Z
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9121ESE | 制造商:Maxim Integrated Products 功能描述:QUAD LVDS LINE RECEIVER WITH FLOW-THROUGH PIN - Bulk |
| MAX9121ESE-T | 制造商:Maxim Integrated Products 功能描述:QUAD LVDS LINE RECEIVER WITH FLOW-THROUGH PIN - Tape and Reel |
| MAX9121EUE | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9121EUE+ | 功能描述:LVDS 接口集成電路 Quad LVDS Line Driver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9121EUE+T | 功能描述:LVDS 接口集成電路 Quad LVDS Line Driver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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