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參數(shù)資料
| 型號： | MAX9121ESE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout |
| 中文描述： | QUAD LINE RECEIVER, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 231K |
| 代理商： | MAX9121ESE |
Board Layout
Because the MAX9121/MAX9122 feature a flow-through
pinout, no special layout precautions are required.
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalk.
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the input LVDS signals
from each other to prevent coupling. Isolate the output
LVCMOS/LVTTL signals from each other to prevent
coupling. Separate the input LVDS signals from the out-
put signals planes with the power and ground planes
for best results.
M
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
_______________________________________________________________________________________
9
IN_+
EN
EN
IN_-
OUT_
DEVICE
UNDER
TEST
1/4 MAX9121/MAX9122
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
S
1
= V
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
S
1
= GND FOR t
PZH
AND t
PHZ
MEASUREMENTS.
GENERATOR
50
C
L
R
L
S
1
V
CC
Figure 4. High-Impedance Delay Test Circuit
Figure 5. High-Impedance Delay Waveforms
1.5V
EN WHEN EN = GND OR OPEN
EN WHEN EN = V
CC
OUTPUT WHEN
V
ID
= -100mV
OUTPUT WHEN
V
ID
= +100mV
1.5V
1.5V
0.5V
0.5V
t
PLZ
t
PHZ
t
PZL
t
PZH
1.5V
3V
0
3V
V
CC
V
OL
V
OH
GND
0
50%
50%
Chip Information
TRANSISTOR COUNT: 1354
PROCESS: CMOS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9121EUE | Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout |
| MAX9122ESE | Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout |
| MAX9122EUE | Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout |
| MAX9121 | Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout |
| MAX9126ESE | Quad LVDS Line Receivers with Integrated Termination |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9121ESE-T | 制造商:Maxim Integrated Products 功能描述:QUAD LVDS LINE RECEIVER WITH FLOW-THROUGH PIN - Tape and Reel |
| MAX9121EUE | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9121EUE+ | 功能描述:LVDS 接口集成電路 Quad LVDS Line Driver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9121EUE+T | 功能描述:LVDS 接口集成電路 Quad LVDS Line Driver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9121EUE-T | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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