參數資料
型號: MAX9125ESE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: Quad LVDS Line Receivers with Integrated Termination
中文描述: QUAD LINE RECEIVER, PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數: 5/12頁
文件大?。?/td> 226K
代理商: MAX9125ESE
M
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(V
CC
= +3.3V,
|
V
ID
|
= 200mV, V
CM
= +1.2V, C
L
= 10pF, frequency = 10MHz, T
A
= +25
°
C, unless otherwise noted (Figures 2 and 3).)
PIN
NAME
IN_-
IN_+
OUT_
FUNCTION
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
Inverting Differential Receiver Inputs
Noninverting Differential Receiver Inputs
LVCMOS/LVTTL Receiver Outputs
4, 12
EN,
EN
Receiver Enable Inputs. When EN = low and
EN
= high, the outputs are disabled and in high
impedance. For other combinations of EN and
EN
, the outputs are active.
8
16
GND
V
CC
Ground
Power Supply Input. Bypass V
CC
to GND with 0.1
μ
F and 0.001
μ
F ceramic capacitors.
Pin Description
2.6
2.5
2.4
2.3
2.2
0
1.0
0.5
COMMON-MODE VOLTAGE (V)
1.5
2.0
2.5
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
M
D
t
PHLD
t
PLHD
50
100
75
150
125
175
200
-40
10
35
-15
60
85
PULSE SKEW vs. TEMPERATURE
M
TEMPERATURE (
°
C)
S
0
900
400
200
100
500
1000
5
15
10
20
25
TRANSITION TIME vs. CAPACITIVE LOAD
M
CAPACITIVE LOAD (pF)
T
t
TLH
t
THL
800
700
600
300
2.2
2.3
2.5
2.4
2.6
3.0
3.2
SUPPLY VOLTAGE (V)
3.3
3.1
3.4
3.5
3.6
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
M
D
t
PHLD
t
PLHD
50
100
75
150
125
175
200
3.0
3.2
SUPPLY VOLTAGE (V)
3.3
3.1
3.4
3.5
3.6
PULSE SKEW vs. SUPPLY VOLTAGE
M
S
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