參數(shù)資料
型號: MAX9126EUE+
廠商: Maxim Integrated Products
文件頁數(shù): 12/12頁
文件大小: 0K
描述: IC QUAD LVDS LINE RCVR 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
類型: 接收器
驅(qū)動器/接收器數(shù): 0/4
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
that have matched differential impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
pick up noise as common mode, which is rejected by
the LVDS receiver.
Termination
The MAX9126 has an integrated termination resistor
connected across the inputs of each receiver. The
value of the integrated resistor is specified in the DC
characteristics.
The MAX9125 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values range between 90
and 132, depend-
ing on the characteristic impedance of the transmission
medium.
When using the MAX9125, minimize the distance
between the input termination resistors and the MAX9125
receiver inputs. Use 1% surface-mount resistors.
Board Layout
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalk.
For LVDS applications, use a four-layer PC board that
provides separate power, ground, LVDS signals, and
output signals. Isolate the input LVDS signals from the
output LVCMOS/LVTTL signals to prevent coupling.
Separate the input LVDS signal plane from the LVC-
MOS/LVTTL output signal plane with the power and
ground planes for best results.
Chip Information
TRANSISTOR COUNT: 940
PROCESS: CMOS
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
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