參數(shù)資料
型號(hào): MAX9156
廠商: Maxim Integrated Products, Inc.
英文描述: Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package
中文描述: 低抖動(dòng)、低噪聲、LVPECL至LVDS電平轉(zhuǎn)換器,SC70封裝
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 149K
代理商: MAX9156
M
Applications Information
Supply Bypassing
Bypass V
CC
with a high-frequency surface-mount
ceramic 0.01μF capacitor as close to the device as
possible.
Differential Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9156. Use controlled-impedance dif-
ferential traces. Ensure that noise couples as common
mode by running the traces within a differential pair
close together.
Maintain the distance within a differential pair to avoid
discontinuities in differential impedance. Avoid 90
°
turns and minimize the number of vias to further prevent
impedance discontinuities.
Cables and Connectors
The LVDS standards define signal levels for intercon-
nect with a differential characteristic impedance and
termination of 100
. Interconnects with a characteristic
impedance and termination of 90
to 132
impedance
are allowed, but produce different signal levels (see
Termination
).
LVPECL signals are typically specified for 50
single-
ended characteristic impedance interconnect terminat-
ed through 50
to V
CC
- 2V.
Use cables and connectors that have matched differen-
tial impedance to minimize impedance discontinuities.
Termination
For point-to-point LVDS links, the termination resistor
should be located at the LVDS receiver input and
match the differential characteristic impedance of the
transmission line.
Each line of a differential LVPECL link should be termi-
nated through 50
to V
CC
- 2V or be replaced by the
Thevinin equivalent.
The LVDS output voltage level depends upon the differ-
ential characteristic impedance of the interconnect and
the value of the termination resistance. The MAX9156 is
guaranteed to produce LVDS output levels into 100
.
With the typical 3.6mA output current, the MAX9156 pro-
duces an output voltage of 360mV when driving a 100
transmission line terminated with a 100
termination
resistor (3.6mA
100
= 360mV). For typical output lev-
els with different loads, see the Differential Output
Voltage vs. Load Resistor typical operating curve.
Chip Information
TRANSISTOR COUNT: 401
PROCESS: CMOS
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
6
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MAX9157 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Quad Bus LVDS Transceiver
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