參數(shù)資料
型號: MAX9174EUB+
廠商: Maxim Integrated Products
文件頁數(shù): 9/14頁
文件大小: 0K
描述: IC SPLITTER 1:2 LVDS 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
類型: 分線器
Tx/Rx類型: LVDS
延遲時間: 2.39ns
電容 - 輸入: 4.5pF
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 25mA
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 管件
產(chǎn)品目錄頁面: 1424 (CN2011-ZH PDF)
MAX9174/MAX9175
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100±1%, CL = 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9174 input common-mode volt-
age, VCM = |VID/2| to (2.4V - |VID/2|), MAX9175 input common-mode voltage VCM = |VID/2| to (VCC - |VID/2|), PD_ = high, TA = -40°C
to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25°C.) (Notes 5, 6, 7)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High-to-Low Propagation Delay
tPHL
Figures 4, 5
1.33
2.38
3.23
ns
Low-to-High Propagation Delay
tPLH
Figures 4, 5
1.33
2.39
3.23
ns
Added Deterministic Jitter
tDJ
Figures 4, 5 (Note 8)
80
ps(P-P)
Added Random Jitter
tRJ
Figures 4, 5
1.0
ps(RMS)
Pulse Skew
tPLH - tPHL
tSKP
Figures 4, 5
10
141
ps
Output-to-Output Skew
tSKOO
Figure 6
14
45
ps
tSKPP1
Figures 4, 5 (Note 9)
0.4
1.3
Part-to-Part Skew
tSKPP2
Figures 4, 5 (Note 10)
1.9
ns
Rise Time
tR
Figures 4, 5
110
257
365
ps
Fall Time
tF
Figures 4, 5
110
252
365
ps
Power-Down Time
tPD
Figures 7, 8
10
13
ns
PD0, PD1 = L
→ H, Figures 7, 8
18
35
s
PD0 = H, PD1 = L
→ H, Figures 7, 8
92
103
Power-Up Time
tPU
PD1 = H, PD0 L
→ H, Figures 7, 8
92
103
ns
Maximum Data Rate
DRMAX
Figures 4, 5,
VOD ≥ 250mV
(Note 11)
800
Mbps
Maximum Switching Frequency
fMAX
Figures 4, 5,
VOD ≥ 250mV (Note 11)
670
MHz
fIN = 670MHz
55
65
Switching Supply Current
ICCSW
fIN = 155MHz
35
44
mA
PRBS Supply Current
ICCPR
DR = 800Mbps, 223 - 1 PRBS input
37
46
mA
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VOD, and VOD.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at
TA = +25°C.
Note 3: Tolerance on all external resistors (including figures) is ±1%.
Note 4: Guaranteed by design.
Note 5: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
Note 6: CL includes scope probe and test jig capacitance.
Note 7: Pulse-generator output for differential inputs IN+, IN- (unless otherwise noted): f = 670MHz, 50% duty cycle, RO = 50, tR =
700ps, and tF = 700ps (0% to 100%). Pulse-generator output for single-ended inputs PD0, PD1: tR = tF = 1.5ns (0.2VCC to
0.8VCC), 50% duty cycle, VOH = VCC + 1.0V settling to VCC, VOL = -1.0V settling to zero, f = 10kHz.
Note 8: Pulse-generator output for tDJ: |VOD| = 0.15V, VOS = 1.25V, data rate 800Mbps, 223 - 1 PRBS, RO = 50, tR = 700ps, and tF
= 700ps (0% to 100%).
Note 9: tSKPP1 is the magnitude of the difference of any differential propagation delays between devices operating under identical
conditions.
Note 10: tSKPP2 is the magnitude of the difference of any differential propagation delays between devices operating over rated con-
ditions.
Note 11: Meets all AC specifications.
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