參數(shù)資料
型號: MAX9180EXT+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/9頁
文件大?。?/td> 0K
描述: IC REPEATER LVDS SC70-6
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 轉(zhuǎn)發(fā)器
Tx/Rx類型: LVDS
延遲時間: 2.0ns
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 10mA
安裝類型: 表面貼裝
封裝/外殼: 6-TSSOP,SC-88,SOT-363
供應(yīng)商設(shè)備封裝: SC-70-6
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX9180EXT+TDKR
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium, as defined by the ANSI/
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other com-
mon communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9180 is a 400Mbps LVDS repeater intended
for high-speed, point-to-point, low-power applications.
The MAX9180 accepts an LVDS input and reproduces
an LVDS signal at the output. This device is capable of
detecting differential signals as low as 50mV and as
high as 1.2V within a 0 to 2.4V input voltage range. The
LVDS standard specifies an input voltage range of 0 to
2.4V referenced to ground.
Fail-Safe
Fail-safe is a feature that puts the output in a known
logic state (differential high) under certain fault condi-
tions. The MAX9180 outputs are differential high when
the inputs are undriven and open, terminated, or shorted
(Table 1).
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
_______________________________________________________________________________________
5
400
450
500
550
600
650
700
750
800
-40
-15
10
35
60
85
TRANSITION TIME
VS.
TEMPERATURE
MAX9180
toc10
TEMPERATURE (°C)
TRANSITION
TIME
(ps)
tTLH, tTHL
0
200
100
400
300
500
600
25
150
DIFFERENTIAL OUTPUT VOLTAGE
VS.
LOAD RESISTOR
MAX9180
toc11
LOAD RESISTOR (
)
DIFFERENTIAL
OUTPUT
VOLTAGE
(mV)
75
50
100
125
Typical Operating Characteristics (continued)
(VCC = 3.3V, RL = 100 ±1%, CL = 10pF,
|VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted. Signal generator output:
frequency = 200MHz, 50% duty cycle, RO = 50, tR = 1.5ns, and tF = 1.5ns (0% to 100%), unless otherwise noted.)
Pin Description
PIN
NAME
FUNCTION
1
OUT-
Inverting LVDS Output
2
GND
Ground
3
IN-
Inverting LVDS Input
4
IN+
Noninverting LVDS Input
5VCC
Power Supply. Bypass VCC to GND
with a 0.01F ceramic capacitor.
6
OUT+
Noninverting LVDS Output
INPUT, VID
OUTPUT, VOD
>50mV
High
<-50mV
Low
50mV
> VID > -50mV
Indeterminate
Undriven open, short, or terminated
High
Note: VID = (IN+ - IN-), VOD = (OUT+ - OUT-)
High = 450mV ≥ VOD ≥ 250mV
Low = -250mV ≥ VOD ≥ -450mV
Table 1. Function Table for LVDS Fail-Safe
Input (Figure 2)
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