參數(shù)資料
型號: MAX9206
廠商: Maxim Integrated Products, Inc.
英文描述: 10-Bit Bus LVDS Deserializers
中文描述: 10位總線LVDS解串器
文件頁數(shù): 4/12頁
文件大小: 179K
代理商: MAX9206
M
10-Bit Bus LVDS Deserializers
4
_______________________________________________________________________________________
Note 1:
Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground
except V
TH
, V
TL
, and V
ID
, which are differential input voltages.
Note 3:
DC parameters are production tested at T
A
= +25°C and guaranteed by design and characterization over operating temper-
ature range.
Note 4:
AC parameters guaranteed by design and characterization.
Note 5:
C
L
includes scope probe and test jig capacitance.
Note 6:
t
RCP
is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequen-
cy of TCLK must be within ±400ppm of the REFCLK frequency.
AC ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= DV
CC
= +3.0V to +3.6V, C
L
= 15pF, differential input voltage
|
V
ID
|
= 0.15V to 1.2V, common-mode voltage V
CM
=
|
V
ID
/2
|
to
2.4V -
|
V
ID
/2
, T
A
= -40
°
C to +85
°
C, unless otherwise noted. Typical values are at AV
CC
= DV
CC
= +3.3V, V
CM
= +1.1V,
|
V
ID
|
= 0.2V,
T
A
= +25
°
C.) (Notes 4, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL Lock Time (from Start of
Sync Patterns)
t
DSR2
PLL locked to stable REFCLK; supply
stable; static input; measured from start
of sync patterns at input to
LOCK
transition low; Figure 8
42 x t
RFCP
ns
LOCK
High-Z to High-State
Delay
t
ZHLK
Figure 7
30
ns
16MHz
40MHz
40MHz
60MHz
1300
720
720
320
MAX9206
Input Jitter Tolerance
t
JT
Figure 9
MAX9208
ps
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