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參數(shù)資料
| 型號(hào)： | MAX9209GUM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable DC-Balanced 21-Bit Serializers |
| 中文描述： | TRIPLE LINE DRIVER, PDSO48 |
| 封裝： | 6.10 MM, MO-153ED, TSSOP-48 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 333K |
| 代理商： | MAX9209GUM |
M
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________
11
data channels is 10. At most, 10 more zeros than ones,
or 10 more ones than zeros, are transmitted. The maxi-
mum DSV for the clock channel is 5. Limiting the DSV
and choosing the correct coupling capacitors maintain
differential signal amplitude and reduce jitter due to
droop on AC-coupled links.
To obtain DC balance on the data channels, the parallel
input data is inverted or not inverted, depending on the
sign of the digital sum at the word boundary. Two com-
plementary bits are appended to each group of 7 paral-
lel input data bits to indicate to the MAX9210/MAX9212/
MAX9214/MAX9216 deserializers whether the data bits
are inverted (Figure 11). The deserializer restores the
original state of the parallel data. The LVDS clock signal
alternates duty cycles of 4/9 and 5/9, which maintains
DC balance. Figure 12 shows the non-DC-balanced
mode inputs mapped to LVDS outputs.
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode volt-
age range by AC-coupling. AC-coupling increases the
DCA0
DCB1
DCA1
DCB2
DCA2
CYCLE N + 1
CYCLE N
CYCLE N - 1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN2
TxIN3
TxIN4
DCA0
TxIN5
TxIN6
DCB0
TxIN9
TxIN10
TxIN11
DCA1
TxIN12
TxIN13
DCB1
TxIN16
TxIN17
TxIN18
DCA2
TxIN19
TxIN20
DCB2
TxIN0
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
DCB0
TxCLK OUT-
TxOUT1
TxOUT0
TxOUT2
TxIN1
TxIN8
TxIN15
TxIN0
TxIN7
TxIN14
TxCLK OUT+
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
2.0V
3.0V
HIGH-Z
DIFFERENTIAL 0
3.6V
V
OD
= 0
V
CC
TxOUT_, TxCLK OUT
TxCLK IN
PWRDWN
TPPLS
Figure 9. PLL Set Time
TxOUT_, TxCLK OUT
TxCLK IN
PWRDWN
HIGH-Z
0.8V
TPDD
Figure 10. Power-Down Delay
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9217 | 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer |
| MAX9217ECM | 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer |
| MAX9217ETM | 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer |
| MAX9232 | Programmable Spread-Spectrum and DC-Balance 21-Bit Deserializer |
| MAX9232EUM | Programmable Spread-Spectrum and DC-Balance 21-Bit Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9209GUM+ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balanced 21-Bit Serializers |
| MAX9209GUM+D | 功能描述:串行器/解串器 - Serdes 21-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9209GUM+TD | 功能描述:串行器/解串器 - Serdes 21-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX920ESA | 功能描述:校驗(yàn)器 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
| MAX920ESA/GG8 | 制造商:Maxim Integrated Products 功能描述:- Bulk |
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