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參數(shù)資料
| 型號： | MAX9217ETM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer |
| 中文描述： | LINE DRIVER, QCC48 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, QFN-48 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 230K |
| 代理商： | MAX9217ETM |
M
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
______________________________________________________________________________________
13
Power-Down and Power-Off
Driving
PWRDWN
low stops the PLL, switches out the
integrated 100
output termination, and puts the output
in high impedance to ground and differentially. With
PWRDWN
≤
0.3V and all LVTTL/LVCMOS inputs
≤
0.3V or
≥
V
CCIN
- 0.3V, supply current is reduced to 50μA or less.
Driving
PWRDWN
high starts PLL lock to PCLK_IN and
switches in the 100
output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100
differen-
tial. The 100
integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that V
OD
= 0V.
If V
CC
= 0, the output resistor is switched out and the LVDS
outputs are high impedance to ground and differentially.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 16,385 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, MOD0, MOD1, PCLK_IN, and
PWRDWN
) are powered from V
CCIN
. V
CCIN
can be
connected to a 1.71V to 3.6V supply, allowing logic
inputs with a nominal swing of V
CCIN
. If no power is
applied to V
CCIN
when power is applied to V
CC
, the
inputs are disabled and
PWRDWN
is internally driven
low, putting the device in the power-down state.
Power-Supply Circuits and Bypassing
The MAX9217 has isolated on-chip power domains. The
digital core supply (V
CC
) and single-ended input supply
(V
CCIN
) are isolated but have a common ground (GND).
The PLL has separate power and ground (V
CCPLL
and
V
CCPLL
GND) and the LVDS input also has separate
power and ground (V
CCLVDS
and V
CCLVDS
GND). The
grounds are isolated by diode connections. Bypass each
V
CC
, V
CCIN
, V
CCPLL
, and V
CCLVDS
pin with high-frequen-
cy, surface-mount ceramic 0.1μF and 0.001μF capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
LVDS Output
The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100
±
1%.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100
. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9217ETM+ | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9217ETM+T | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9217ETM+T&R | 制造商:Maxim Integrated Products 功能描述:27-BIT, 3MHZ-TO-35MHZ DC-BALANCED LVDS SERIALIZER - Tape and Reel |
| MAX9217ETM-T | 制造商:Maxim Integrated Products 功能描述:27-BIT 3MHZ-TO-35MHZ DC-BALANCED LVDS SERIALI - Tape and Reel |
| MAX9217EVKIT+ | 功能描述:界面開發(fā)工具 MAX9217/18 Eval Kit RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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