- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11685 > MAX9218ECM+T (Maxim Integrated Products)IC DESERIALIZER LVDS 48-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MAX9218ECM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER LVDS 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 700Mbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 27 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
10
______________________________________________________________________________________
Detailed Description
The MAX9218 DC-balanced deserializer operates at a
parallel clock frequency of 3MHz to 35MHz, deserializ-
ing video data to the RGB_OUT[17:0] outputs when the
data enable output DE_OUT is high, or control data to
the CNTL_OUT[8:0] outputs when DE_OUT is low. The
video phase words are decoded using 2 overhead bits,
EN0 and EN1. Control phase words are decoded with 1
overhead bit, EN0. Encoding, performed by the
MAX9217 serializer, reduces EMI and maintains DC
balance across the serial cable. The serial input word
formats are shown in Table 1 and Table 2.
Control data inputs C0 to C4, each repeated over 3 seri-
al bit times by the serializer, are decoded using majority
voting. Two or three bits at the same state determine the
state of the recovered bit, providing single bit-error tol-
erance for C0 to C4. The state of C5 to C8 is deter-
mined by the level of the bit itself (no voting is used).
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two
capacitors are sufficient for isolation, but four capaci-
tors—two at the serializer output and two at the deseri-
alizer input—provide protection if either end of the
cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
The MAX9217 serializer can also be DC-coupled to the
MAX9218 deserializer. Figure 10 is the AC-coupled
serializer and deserializer with two capacitors per link,
and Figure 11 is the AC-coupled serializer and deseri-
alizer with four capacitors per link.
Applications Information
Selection of AC-Coupling Capacitors
See Figure 12 for calculating the capacitor values for
AC-coupling, depending on the parallel clock frequen-
cy. The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1F capacitors.
Termination and Input Bias
The IN+ and IN- LVDS inputs are internally connected
to +1.2V through 35k
Ω (min) to provide biasing for AC-
coupling (Figure 1). Assuming 100
Ω interconnect, the
LVDS input can be terminated with a 100
Ω resistor.
Match the termination to the differential impedance of
the interconnect.
Use a Thevenin termination, providing 1.2V bias, on an
AC-coupled link in noisy environments. For intercon-
nect with 100
Ω differential impedance, pull each LVDS
line up to VCC with 130
Ω and down to ground with 82Ω
at the deserializer input (Figure 10 and Figure 11). This
termination provides both differential and common-
mode termination. The impedance of the Thevenin ter-
mination should be half the differential impedance of
the interconnect and provide a bias voltage of 1.2V.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
EN0
EN1
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 1. Serial Video Phase Word Format
0123456789
10
11
12
13
14
15
16
17
18
19
EN0
C0C0C0C1C1C1C2C2C2C3C3C3
C4C4C4C5C6C7C8
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.
Table 2. Serial Control Phase Word Format
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9220EUM+D | IC DESERIALIZER PROG 48TSSOP |
| MAX9220EUM+ | IC DESERIALIZER PROG 48TSSOP |
| MAX9210EUM+D | IC DESERIALIZER PROG 48TSSOP |
| 031-5999-RFX | CONN PLUG BNC CRIMP LMR240 |
| MAX9248GCM/V+T | IC DESERIALIZR LVDS 27BIT 48TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9218ETM | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9218ETM+ | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9218ETM+T | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9218ETM+T&R | 制造商:Maxim Integrated Products 功能描述:27-BIT, 3MHZ-TO-35MHZ DC-BALANCED LVDS SERIALIZER - Tape and Reel |
| MAX9218ETM-T | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。