參數(shù)資料
型號(hào)： MAX9220EUM+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/17頁(yè)
文件大小： 0K
描述： IC DESERIALIZER PROG 48TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 39
功能： 解串器
數(shù)據(jù)速率： 1.785Gbps
輸入類(lèi)型： LVDS
輸出類(lèi)型： LVTTL，LVCMOS
輸入數(shù)： 3
輸出數(shù)： 21
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 48-TSSOP
包裝： 管件
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________
11
series capacitors is (C x (RT + RO))/2 (Figure 12). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO))/4 (Figure 13).
RT is required to match the transmission line imped-
ance (usually 100
Ω) and RO is determined by the LVDS
driver design (the minimum differential output resis-
tance of 78
Ω for the MAX9209/MAX9213 serializers is
used in the following example). This leaves the capaci-
tor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = - (2 x tB x DSV)/(ln (1 - D) x (RT + RO)) (Eq 1)
where:
C = AC-coupling capacitor (F).
tB = bit time (s).
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
RT = termination resistor (
Ω).
RO = output resistance (
Ω).
Equation 1 is for two series capacitors (Figure 12). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 13).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = - (2 x tB x DSV)/(ln (1 - D) x (RT + RO))
C = - (2 x 13.9ns x 10)/(ln (1 - 0.02) x (100
Ω + 78Ω))
C = 0.0773F
Jitter due to droop is proportional to the droop and
transition time:
tJ = tT x D (Eq 2)
where:
tJ = jitter (s).
tT = transition time (s) (0 to 100%).
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
tJ = 1ns x 0.02
tJ = 20ps
(7 + 2):1
1:(9 - 2)
7
100
Ω
(7 + 2):1
1:(9 - 2)
7
100
Ω
(7 + 2):1
1:(9 - 2)
7
100
Ω
PLL
100
Ω
MAX9209
MAX9213
MAX9210
MAX9214
MAX9220
MAX9222
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
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參數(shù)描述
MAX9220EUM/V+ 功能描述:串行器/解串器 - Serdes Programmable DC-Bal 21-Bit Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9220EUM/V+T 功能描述:串行器/解串器 - Serdes Programmable DC-Bal 21-Bit Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9220EUM+ 功能描述:串行器/解串器 - Serdes DC-Balanced Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9220EUM+D 功能描述:串行器/解串器 - Serdes DC-Balanced Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9220EUM+T 功能描述:串行器/解串器 - Serdes DC-Balanced Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
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