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參數(shù)資料
| 型號： | MAX9224ETI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 0K |
| 描述： | IC DESERIALIZER LP 28-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 220Mbps |
| 輸入類型： | 并聯(lián) |
| 輸出類型： | 并聯(lián) |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 22 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
MAX9223/MAX9224
Applications Information
PCLKIN Latch Edge
The parallel data input of the MAX9223 serializer is
latched on the rising edge of PCLKIN. Figure 3 shows
the serializer input timing.
PCLKOUT Strobe
The serial-data output of the MAX9224 deserializer is
valid on the rising edge of PCLKOUT. Figure 4 shows
the deserializer output timing.
Power-Down and Power-Up
Driving PWRDN low puts the MAX9223 in power-down
mode and sends a pulse to power down the MAX9224. In
power-down mode, the DLL is stopped, SDO+/SDO- are
high impedance to ground and differential, and the LCDS
link is weakly biased around VDD - 0.8V. With PWRDN
and all inputs low, the combined MAX9223/MAX9224
supply current is reduced to 3.5A or less.
Driving PWRDN high starts DLL lock to PCLKIN and ini-
tiates a MAX9224 power-up sequence. The MAX9223
LCDS output is not driven until the DLL locks. 4096
clock cycles are required for the power-up and link
synchronization, before valid DIN can be latched. See
Figure 6 for an overall power-up and power-down tim-
ing diagram. For normal operation, PCLKIN must be
running and settled before driving PWRDN high.
If VDD = 0, the LCDS outputs are high impedance to
ground and differential.
Ground-Shift Tolerance
The MAX9223/MAX9224 are designed to function nor-
mally in the event of a slight shift in ground potential.
However, the MAX9224 deserializer ground must be
within ±0.2V relative to the MAX9223 serializer ground
to maintain proper operation.
MAX9224 Output Buffer Supply (VDDO)
The MAX9224 parallel outputs are powered from VDDO,
which accepts a +1.71V to +3.465V supply, allowing
direct interface to inputs with 1.8V to 3.3V logic levels.
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
10
______________________________________________________________________________________
DIN[21:0]
PCLK IN
DIN
0
1
2
3
9
10
11
12
13
14
EXAMPLE
INPUT
1
0
1
00
1
PARALLEL DATA INPUT
LCDS SERIAL DATA OUTPUT FOR EXAMPLE INPUT (SD0
±)
NOTE: THERE IS NO TRANSITION BETWEEN OH BITS.
20
21
1
0
*INTERNALLY PREPENDED BIT—ALWAYS 0.
G*
1
0
1
0
1
0
1
OH
Figure 5. Multilevel LCDS Output Representation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9224EVKIT | 制造商:Maxim Integrated Products 功能描述:22-BIT LOW-POWER 5MHZ TO 10MHZ SE - Rail/Tube |
| MAX9225 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset |
| MAX9225ETE | 制造商:Maxim Integrated Products 功能描述:10-BIT LOW-POWER 10MHZ TO 20MHZ S - Rail/Tube |
| MAX9225ETE+ | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9225ETE+T | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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