M
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
12
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Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended.
ESD Protection
The MAX9234/MAX9236/MAX9238 ESD tolerance is
rated for IEC 61000-4-2 Human Body Model and ISO
10605 standards. IEC 61000-4-2 and ISO 10605 specifiy
ESD tolerance for electronic systems. The Human Body
Model discharge components are C
S
= 100pF and R
D
=
1.5k
Ω
(Figure 12). For the Human Body Model, all pins
are rated for ±5kV contact discharge. The ISO 10605 dis-
charge components are C
S
= 330pF and R
D
= 2k
Ω
(Figure 13). For ISO 10605, the LVDS outputs are rated
for ±8kV contact and ±25kV air discharge. The IEC
61000-4-2 discharge components are C
S
= 150pF and
R
D
= 330
Ω
(Figure 14). For IEC 61000-4-2, the LVDS
inputs are rated for ±8kV Contact Discharge and ±15kV
Air-Gap Discharge.
5V Tolerant Input
PWRDWN
is 5V tolerant and is internally pulled down to
GND.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
V
CCO
Output Supply and Power Dissipation
The outputs have a separate supply (V
CCO
) for interfacing
to systems with 1.8V to 5V nominal input-logic levels. The
DC Electrical Characteristics
table gives the maximum
supply current for V
CCO
= 3.6V with 8pF load at several
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
tal supply current for V
CCO
other than 3.6V with the same
8pF load and worst-case pattern can be calculated using:
I
I
= C
T
V
I
0.5f
C
x 21 (data outputs)
+ C
T
V
I
f
C
x 1 (clock output)
where:
I
I
= incremental supply current.
C
T
= total internal (C
INT
) and external (C
L
) load capaci-
tance.
V
I
= incremental supply voltage.
f
C
= output clock-switching frequency.
The incremental current is added to (for V
CCO
>
3.6V)
or subtracted from (for V
CCO
<
3.6V) the
DC Electrical
Characteristics
table maximum supply current. The
internal output buffer capacitance is C
INT
= 6pF. The
worst-case pattern-switching frequency of the data out-
puts is half the switching frequency of the output clock.
In the following example, the incremental supply current is
calculated for V
CCO
= 5.5V, f
C
= 34MHz, and C
L
= 8pF:
V
I
= 5.5V - 3.6V = 1.9V
C
T
= C
INT
+ C
L
= 6pF + 8pF = 14pF
Figure 13. ISO 10605 Contact Discharge ESD Test Circuit
Figure 12. Human Body ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
R1
1M
Ω
R2
1.5k
Ω
C
S
100pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
R1
50
Ω
TO 100
Ω
R2
2k
Ω
C
S
330pF
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50
Ω
TO 100
Ω
R
D
330
Ω
C
S
150pF