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參數(shù)資料
| 型號： | MAX9236 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers |
| 中文描述： | 熱插拔、21位、直流平衡、LVDS解串器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 199K |
| 代理商： | MAX9236 |
M
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
______________________________________________________________________________________
11
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = - (2 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
)) (Eq 1)
where:
C = AC-coupling capacitor (F).
t
B
= bit time (s).
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
R
T
= termination resistor (
Ω
).
R
O
= output resistance (
Ω
).
Equation 1 is for two series capacitors (Figure 10). The
bit time (t
B
) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 11).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = - (2 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
))
C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100
Ω
+ 78
Ω
))
C = 0.0773μF
Jitter due to droop is proportional to the droop and
transition time:
t
J
= t
T
x D (Eq 2)
where:
t
J
= jitter (s).
t
T
= transition time (s) (0 to 100%).
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
t
J
= 1ns x 0.02
t
J
= 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 11) is:
C = - (4 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
)) (Eq 3)
Input Bias and Frequency Detection
The inverting and noninverting LVDS inputs are internally
connected to +1.2V through 42k
Ω
(min) to provide bias-
ing for AC-coupling (Figure 1). A frequency-detection
circuit on the clock input detects when the input is not
switching, or is switching at low frequency. In this case,
all outputs are driven low. To prevent switching due to
noise when the clock input is not driven, bias the clock
input to differential +15mV by connecting a 10k
Ω
±1%
pullup resistor between the noninverting input and V
CC
,
and a 10k
Ω
±1% pulldown resistor between the invert-
ing input and ground. These bias resistors, along with
the 100
Ω
±1% tolerance termination resistor, provide
+15mV of differential input.
Unused LVDS Data Inputs
At each unused LVDS data input, pull the inverting input
up to V
CC
using a 10k
Ω
resistor, and pull the noninverting
input down to ground using a 10k
Ω
resistor. Do not con-
nect a termination resistor. The pullup and pulldown resis-
tors drive the corresponding outputs low and prevent
switching due to noise.
PWRDWN
Driving
PWRDWN
low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50μA or less. Driving
PWRDWN
high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by
PWRDWN
. Wait 100ns between disabling one
deserializer (driving
PWRDWN
low) and enabling the
second one (driving
PWRDWN
high) to avoid con-
tention of the bused outputs.
Input Clock and PLL Lock Time
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to
PWRDWN
, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock-time specification. When the PLL is locking, the
outputs are low.
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
V
CC
, V
CCO
, PLL V
CC
, and LVDS V
CC
pin with high-fre-
quency, surface-mount ceramic 0.1μF and 0.001μF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100
Ω
. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9236EUM | 制造商:Maxim Integrated Products 功能描述:HOT-SWAPPABLE, 21-BIT, DC-BALANCED LVDS DESER - Rail/Tube |
| MAX9236EUM+D | 功能描述:接口 - 專用 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| MAX9236EUM+TD | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9236EUM-D | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| MAX9236EUM-T | 制造商:Maxim Integrated Products 功能描述:HOT-SWAPPABLE, 21-BIT, DC-BALANCED LVDS DESER - Tape and Reel |
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