II
參數(shù)資料
型號: MAX9238EUM+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/15頁
文件大?。?/td> 0K
描述: IC DESERIALIZER 21BIT 48TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 解串器
數(shù)據(jù)速率: 1.386Gbps
輸入類型: LVDS
輸出類型: LVTTL,LVCMOS
輸入數(shù): 3
輸出數(shù): 21
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
13
Maxim Integrated
where:
II = CTVI 0.5FC x 21 (data outputs) + CTVIfC x 1 (clock
output).
II = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
34MHz).
II = 9.5mA + 0.9mA = 10.4mA.
The maximum supply current in DC-balanced mode for
VCC = VCCO = 3.6V at fC = 34MHz is 106mA (from the
DC Electrical Characteristics table). Add 10.4mA to get
the total approximate maximum supply current at VCCO
= 5.5V and VCC = 3.6V.
If the output supply voltage is less than VCCO = 3.6V,
the reduced supply current can be calculated using the
same formula and method.
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power-dissipation rating. Do not exceed
the maximum package power-dissipation rating. See
the
Absolute Maximum Ratings for maximum package
power-dissipation capacity and temperature derating.
Rising- or Falling-Edge Output Strobe
The MAX9234 has a rising-edge output strobe, which
latches the parallel output data into the next chip on the
rising edge of RxCLK OUT. The MAX9236/MAX9238
have a falling-edge output strobe, which latches the
parallel output data into the next chip on the falling
edge of RxCLK OUT. The deserializer output strobe
polarity does not need to match the serializer input
strobe polarity. A deserializer with rising- or falling-
edge output strobe can be driven by a serializer with a
rising-edge input strobe.
RxIN0+
LVDS DATA
RECEIVER 0
RxIN0-
STROBE
DATA
CHANNEL 0
RxOUT0–6
SERIAL-TO-
PARALLEL
CONVERTER
RxIN1+
LVDS DATA
RECEIVER 1
RxIN1-
STROBE
DATA
CHANNEL 1
RxOUT7–13
SERIAL-TO-
PARALLEL
CONVERTER
RxIN2+
LVDS DATA
RECEIVER 2
RxIN2-
STROBE
DATA
CHANNEL 2
RxOUT14–20
SERIAL-TO-
PARALLEL
CONVERTER
RxCLK IN+
LVDS CLOCK
RECEIVER
RxCLK IN-
9x
PLL
RxCLK OUT
REFERENCE
CLOCK
GENERATOR
PWRDWN
Functional Diagram
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