參數(shù)資料
型號(hào): MAX9249GCM/V+
廠商: Maxim Integrated Products
文件頁數(shù): 10/36頁
文件大?。?/td> 0K
描述: IC SERIALIZER GMSL LVDS 48TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 250
功能: 串行器
數(shù)據(jù)速率: 2.5Gbs
輸入類型: LVDS
輸出類型: 串行
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 管件
18 _____________________________________________________________________________________
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
the embedded serial clock and then samples, decodes,
and descrambles before outputting the data. Figures
15 and 16 show the serial-data packet format before
scrambling and 8B/10B coding. In 3-channel or 4-chan-
nel mode, 21 or 28 bits come from the RXIN_ _ LVDS
inputs. Control bits can be mapped to DIN27 and DIN28
in 4-channel mode. The audio channel bit (ACB) con-
tains an encoded audio signal derived from the three I2S
inputs (SD/CNTL0, SCK, and WS). The forward control-
channel (FCC) bit carries the forward control data. The
last bit (PCB) is the parity bit of the previous 23 or 31 bits.
Reserved Bit (RES)
In 4-channel mode, the MAX9249 serializes all bits of all
four lanes including RES by default. Set DISRES (D4 of
Register 0x0D) to 1 to map CNTL1 to DIN27 instead of
RES.
Reverse Control Channel
The MAX9249 uses the reverse control channel to
receive I2C/UART and interrupt signals from the GMSL
deserializer in the opposite direction of the video stream.
The reverse control channel and forward video data
coexist on the same twisted pair forming a bidirectional
link. The reverse control channel operates independently
from the forward control channel. The reverse control
channel is available 500Fs after power-up. The MAX9249
temporarily disables the reverse control channel for
350Fs after starting/stopping the forward serial link.
Data-Rate Selection
The MAX9249 uses the DRS input to set the RXCLKIN_
frequency. Set DRS high for an RXCLKIN_ frequency of
6.25MHz to 12.5MHz (4-channel mode) or 8.33MHz to
16.66MHz (3-channel mode). Set DRS low for normal
operation with an RXCLKIN_ frequency of 12.5MHz
to 78MHz (4-channel mode) or 16.66MHz to 104MHz
(3-channel mode).
Figure 14. VESA Standard Panel Clock and Bit Assignment
Figure 15. 3-Channel Mode Serial Link Data Format
R1
CYCLE N-1
CYCLE N
RXIN0+/RXIN0-
RXCLKIN+
RXCLKIN-
RXIN1+/RXIN1-
RXIN2+/RXIN2-
R0
G0
R5
R4
R3
R2
R1
R0
G2
G1
B1
B0
G5
G4
G3
G2
G1
B3
B2
DE
VS
HS
B5
B4
B3
B2
RXIN3+/RXIN3-
R7
R6
RES
B7
B6
G7
G6
R7
R6
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
SET ACCORDING TO VESA STANDARD PANEL BITMAP.
DIN0
LVDS
DATA
(3 CHANNELS)
DIN1
DIN17 DIN18 DIN19 DIN20
ACB
FCC
PCB
24 BITS
AUDIO
CHANNEL BIT
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
R0
R1
B5
HS
VS
DE
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