參數(shù)資料
型號: MAX9390EHJ+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/14頁
文件大?。?/td> 0K
描述: IC CROSSPOINT SWITCH DUAL 32TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 交叉點(diǎn)開關(guān)
電路: 2 x 2:2
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
電流 - 電源: 68mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(5x5)
包裝: 帶卷 (TR)
MAX9390/MAX9391
Applications Information
Differential Inputs
The MAX9390/MAX9391 inputs accept any differential
signaling standard within the specified common-mode
voltage range. The fail-safe feature detects common-
mode input signal levels and generates a differential
output low condition for undriven inputs or when the
common-mode voltage exceeds the specified range.
Leave unused inputs unconnected or connect to VCC
for the MAX9390 or to GND for the MAX9391.
Differential Outputs
The output common-mode voltage is not properly
established if the LVDS output is higher than 0.6V when
the supply voltage is ramping up at power-on. This
condition can occur when an LVDS output drives an
LVDS input on the same chip. To avoid this situation for
the MAX9390/MAX9391, connect a 10k
Ω resistor from
the noninverting output (OUT_) to ground, and connect
a 10k
Ω resistor from the inverting output (OUT_) to
ground. These pulldown resistors keep the output
below 0.6V when the supply is ramping up (Figure 8).
Expanding the Number of LVDS Output
Ports
Cascade devices to make larger switches. Consider
the total propagation delay and total jitter when deter-
mining the maximum allowable switch size.
Power-Supply Bypassing
Bypass each VCC to GND with high-frequency surface-
mount ceramic 0.1F and 0.01F capacitors in parallel
as close to the device as possible. Install the 0.01F
capacitor closest to the device.
Differential Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9390/MAX9391. Connect each input
and output to a 50
Ω characteristic impedance trace.
Maintain the distance between differential traces and
eliminate sharp corners to avoid discontinuities in dif-
ferential impedance and maximize common-mode
noise immunity. Minimize the number of vias on the dif-
ferential input and output traces to prevent impedance
discontinuities. Reduce reflections by maintaining the
50
Ω characteristic impedance through connectors and
across cables. Minimize skew by matching the electri-
cal length of the traces.
Output Termination
Terminate LVDS outputs with a 100
Ω resistor between
the differential outputs at the receiver inputs. LVDS out-
puts require 100
Ω termination for proper operation.
Ensure that the output currents do not exceed the cur-
rent limits specified in the Absolute Maximum Ratings.
Observe the total thermal limits of the MAX9390/
MAX9391 under all operating conditions.
Cables and Connectors
Use matched differential impedance for transmission
media. Use cables and connectors with matched differ-
ential impedance to minimize impedance discontinu-
ities. Avoid the use of unbalanced cables. Balanced
cables such as twisted pair offer superior signal quality
and tend to generate less EMI due to canceling effects.
Board Layout
Use a four-layer printed circuit (PC) board providing
separate signal, power, and ground planes for high-
speed signaling applications. Bypass VCC to GND as
close to the device as possible. Install termination
resistors as close to receiver inputs as possible. Match
the electrical length of the differential traces to minimize
signal skew.
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
10
______________________________________________________________________________________
Table 1. Input/Output Function Table
_SEL0
_SEL1
OUT_0 /
OUT_0
OUT_1 /
OUT_1
MODE
0
IN_0 / IN_0
1:2 splitter
0
1
IN_0 / IN_0
IN_1 / IN_1
Repeater
1
0
IN_1 / IN_1
IN_0 / IN_0
Switch
1
IN_1 / IN_1
1:2 splitter
100
Ω DIFFERENTIAL
TRANSMISSION LINE
100
Ω
TERMINATION
RESISTOR
10k
Ω
GND
10k
Ω
OUT_
MAX9390
MAX9391
Figure 8. Pulldown Resistor Configuration for LVDS Outputs
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