參數(shù)資料
型號: MAX9450EHJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: High-Precision Clock Generators with Integrated VCXO
中文描述: 9450 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 5 X 5 MM, 1 MM HEIGHT, MS-026-AAA-HD, TQFP-32
文件頁數(shù): 6/18頁
文件大?。?/td> 323K
代理商: MAX9450EHJ
M
High-Precision Clock Generators
with Integrated VCXO
6
_______________________________________________________________________________________
Pin Description
PIN
1
NAME
LOCK
FUNCTION
Lock Indicator.
LOCK
goes low when the PLL locks.
LOCK
is high when the PLL is not locked.
2, 3
S E L0, S E L1
INO_ and IN1_ Select Inputs. Drive SEL0 high to activate IN0; drive SEL1 high to activate IN1. Driving SEL0
and SEL1 low disables the corresponding input. A 165k
Ω
pullup resistor pulls SEL0 and SEL1 up to V
DD
.
Differential Reference Input Pair. IN0+ and IN0- accept LVPECL, LVDS, and LVCMOS signals.
4, 5
IN0+, IN0-
6, 25
V
DD
Digital Power Supply. Connect a 2.4V to 3.6V power supply to V
DD
. Bypass V
DD
to GND with a 0.1μF
capacitor.
7, 8
9
10
11
12
13
IN1+, IN1-
INT
MR
GND/
CS
SCL
SDA
Differential Reference Input Pair. IN1+ and IN1- accept LVPECL, LVDS, and LVCMOS signals.
Reference Input Condition Indicator. A high indicates a failed reference.
Master Reset. Drive MR high to reset all I
2
C registers to their default state and INT to zero.
Ground and Chip-Select Input. Connect to GND in I
2
C mode. This is the chip-select input in SPI mode.
Clock Input. SCL is the clock input in I
2
C bus mode and SPI bus mode.
Data Input. SDA is the data input in I
2
C bus mode and SPI bus mode.
I
2
C Address Selection. Drive AD0 and AD1 high to convert the serial interface from I
2
C to SPI. GND/
CS
becomes
CS
. See Table 3 for the unique addresses list.
14, 15
AD0, AD1
16
CMON
Clock Monitor. Drive
CMON
low to enable the clock monitor. Drive
CMON
high to disable the clock monitor.
17
OE
Output Enable Input. Drive
OE
low to enable the clock outputs. Driving
OE
high disables the clock outputs,
and the outputs go high impedance. An internal 165k
Ω
pullup resistor pulls
OE
up to V
DD
.
18, 24
V
DDQ
Clock-Output Power Supply. Connect a 2.4V to 3.6V power supply to V
DDQ
for the MAX9450 and MAX9452.
Connect a 1.5V power supply to V
DDQ
for the MAX9451. Connect a 0.1μF bypass capacitor from V
DDQ
to
GND.
19, 20
CLK0-,
CLK0+
Differential Clock Output 0. The MAX9450 features LVPECL outputs. The MAX9451 features HSTL outputs
and the MAX9452 features LVDS outputs.
21
GND
Digital GND
22, 23
CLK1-,
CLK1+
Differential Clock Output 1. The MAX9450 features LVPECL outputs. The MAX9451 features HSTL outputs,
and the MAX9452 features LVDS outputs.
26, 27
X1, X2
Reference Crystal Input. Connect the reference crystal from X1 to X2.
28
V
DDA
Anal og P ow er S up p y. C onnect a 2.4V to 3.6V p ow er sup p y to V
D D A
. Byp ass V
D D A
to GN D A w h a 0.1μF
cap aci or
29, 30
31
LP1, LP2
GNDA
External Loop Filter. Connect an RC circuit between LP1 and LP2. See the
External Loop Filter
section.
Analog Ground
32
RJ
Charge-Pump Set Current. Connect an external resistor to GND to set the charge-pump current. See
Table 11.
EP
EP
Exposed Paddle. Connect to ground.
相關(guān)PDF資料
PDF描述
MAX9450_07 High-Precision Clock Generators with Integrated VCXO
MAX9451EHJ High-Precision Clock Generators with Integrated VCXO
MAX9452EHJ High-Precision Clock Generators with Integrated VCXO
MAX9471 Multiple-Output Clock Generators with Dual PLLs and OTP
MAX9471ETP Multiple-Output Clock Generators with Dual PLLs and OTP
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