參數(shù)資料
型號： MAX9451EHJ
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 時鐘及定時
英文描述： High-Precision Clock Generators with Integrated VCXO
中文描述： 9451 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 5 X 5 MM, 1 MM HEIGHT, MS-026-AAA-HD, TQFP-32
文件頁數(shù)： 4/18頁
文件大?。?/td> 323K
代理商： MAX9451EHJ
Note 1:
All timing AC electrical characteristics and timing specifications are guaranteed by design and not production tested.
Note 2:
The VCXO tracks the input clock frequency by ±60ppm.
Note 3:
A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined regions of SCL’s
falling edge.
Note 4:
C
B
= total capacitance of one bus line in pF. Tested with C
B
= 400pF.
Note 5:
Input filters on SDA and SCL suppress noise spikes less than 50ns.
PARAMETER
SYMBOL
f
SCL
t
CSS
t
DS
t
DH
t
CSH
t
CSW
CONDITIONS
MIN
TYP
MAX
2
UNITS
MHz
ns
ns
ns
ns
ns
Serial-Clock Frequency
CS
Fall to CLK Rise Setup Time
DIN Setup Time
DIN Hold Time
CLK High to
CS
High
CS
Pulse-High Time
12.5
12.5
0
0
20
SERIAL SPI INTERFACE TIMING CHARACTERISTICS
(VDD= 2.4V to 3.6V, TA= -40°C to +85°C. See Figure 7 for the timing parameters definition.)
M
High-Precision Clock Generators
with Integrated VCXO
4
_______________________________________________________________________________________
PARAMETER
SYMBOL
f
SCL
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
Serial Clock
Bus Free Time Between STOP and
START Conditions
t
BUF
1.3
μs
Rep eated H ol d Ti m e S TART C ond i on
Rep eated S TART C ond i on S etup Ti m e
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock-Low Period
SCL Clock-High Period
Maximum Receive SCL/SDA Rise Time
t
HD,STA
t
SU,STA
t
SU,STO
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
R
0.6
0.6
0.6
100
100
1.3
0.7
μs
μs
μs
ns
ns
μs
μs
ns
(Note 3)
300
Minimum Receive SCL/SDA Rise Time
t
R
(Note 4)
20
+ 0.1 x C
b
300
ns
Maximum Receive SCL/SDA Fall Time
t
F
ns
Minimum Receive SCL/SDA Fall Time
t
F
(Note 4)
20
+ 0.1 x C
b
ns
Fall Time of SDA, Transmitting
t
F,TX
(Note 4)
20
+ 0.1C
b
0
250
ns
Pulse Width of Suppressed Spike
Capacitive Load for Each Bus Line
t
SP
C
B
(Note 5)
(Note 4)
50
400
ns
pF
SERIAL I
2
C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS
(VDD= 2.4V to 3.6V, TA= -40°C to +85°C. See Figure 4 for the timing parameters definition.)
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參數(shù)描述
MAX9451EHJ+ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 High-Precision Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MAX9451EHJ+T 功能描述:時鐘發(fā)生器及支持產(chǎn)品 High-Precision Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MAX9451EHJ-T 功能描述:時鐘發(fā)生器及支持產(chǎn)品 High-Precision Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MAX9451EVKIT+ 制造商:Microsemi Corporation 功能描述:MAX9451 EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX9451 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX9451
MAX9452EHJ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 High-Precision Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
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