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參數(shù)資料
| 型號： | MAX9485ETP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR AUD 20-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 75 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 73.728MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 20-TQFN-EP（4x4） |
| 包裝： | 管件 |
SDA line operates as both an input and an open-drain
output. A pullup resistor, typically 4.7k
Ω, is required on
SDA. The SCL line operates only as an input. A pullup
resistor, typically 4.7k
Ω, is required on SCL if there are
multiple masters on the 2-wire bus, or if the master in a
single-master system has an open-drain SCL output.
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
idle. The active master signals the beginning of a trans-
mission with a START (S) condition by transitioning
SDA from high to low while SCL is high. After communi-
cation, the MAX9485 issues a STOP (P) condition by
transitioning SDA from low to high while SCL is high,
freeing the bus for another transmission (Figure 5). If a
START or STOP occurs while a bus transaction is in
progress, then it terminates the transaction.
Data Transfer and Acknowledge
Following the START condition, each SCL clock pulse
transfers 1 bit. For the MAX9485 interface, between a
START and a STOP, 18 bits are transferred on the
2-wire bus. The first 7 bits are for the device address.
Bit 8 indicates the writing (low) or reading (high) opera-
tion (R/W). Bit 9 is the ACK for the address and opera-
tion type. Bits 10 though 17 form the data byte. Bit 18 is
the ACK for the data byte. The master always transfers
the first 8 bits (address + R/W). The slave (MAX9485)
can receive the data byte from the bus or transfer it to
the bus from the internal register. The ACK bits are
transmitted by the address or data recipient. A low
ACK bit indicates a successful transfer (Acknowledge),
a high ACK bit indicates an unsuccessful transfer (Not
Acknowledge). Figure 6 shows the structure of the data
transfer. During a write operation, if more synchronous
data is transferred, it overwrites the data in the register.
During a read operation, if more clocks are reset on
SCL, the SDA continues to respond to the register data.
MAX9485
Programmable Audio Clock Generator
______________________________________________________________________________________
11
C3
C2
OUTPUT SCALING FACTOR
0
256
0
1
384
1
0
768
1
Reserved
Table 13. Frequency Scaling Factors
C1
C0
SAMPLING FREQUENCY (kHz)
00
12
01
32
1
0
44.1
11
48
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
Table 14. Sampling Frequency Selection
Note: (C1, C0) = (0, 0) and C4 = 1 (double) is not a proper selec-
tion. However, when set, it selects 12kHz sampling frequency.
Figure 5. Start and Stop Conditions
S
SLAVE ADDRESS
7 BITS
R/W
A
A = ACK; A = 0: ACKNOWLEDGE, A = 1: NOT ACKNOWLEDGE
S = START CONDITION
P = STOP CONDITION
MASTER-WRITE DATA STRUCTURE
MASTER TRANSFERS TO SLAVE
SLAVE TRANSFERS TO MASTER
MASTER-READ DATA STRUCTURE
DATA
8 BITS
P
A
R/W
SLAVE ADDRESS
7 BITS
S
DATA
8 BITS
P
A
Figure 6. Serial Interface Data Structure
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9485ETP+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Programmable Audio Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9485ETP+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Programmable Audio Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9485ETP-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Programmable Audio Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9485EUP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9485EUP+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Programmable Audio Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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