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參數(shù)資料
| 型號： | MAX9598CTL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH DUAL SCART 40TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 功能： | 開關(guān) |
| 電路： | 2 x SCART |
| 導(dǎo)通狀態(tài)電阻： | 7 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V，±11.4 V ~ 12.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX9598
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 7). A START
condition from the master signals the beginning of a
transmission to the MAX9598. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9598 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the 7 MSBs (most sig-
nificant bits) followed by the R/W(read/write) bit. Set
the R/W bit to 1 to configure the MAX9598 to read
mode. Set the R/W bit to 0 to configure the MAX9598 to
write mode. The slave address is always the first byte
of information sent to the MAX9598 after a START or a
REPEATED START condition. The MAX9598 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the MAX9598.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9598 uses to handshake receipt of each byte of
data when in write mode (see Figure 8). The MAX9598
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a
receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master may retry communication. The master
pulls down SDA during the 9th clock cycle to acknowl-
edge receipt of data when the MAX9598 is in read mode.
An acknowledge is sent by the master after each read
byte to allow data transfer to continue. A not acknowl-
edge is sent when the master reads the final byte of data
from the MAX9598, followed by a STOP condition.
Low-Power Audio/Video Switch for
Dual SCART Connectors
18
______________________________________________________________________________________
SCL
SDA
SSr
P
Figure 7. START, STOP, and REPEATED START Conditions
1
SCL
START
CONDITION
SDA
28
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 8. Acknowledge
Table 3. Slave Address
DEV_ADDR
B7
B6
B5
B4
B3
B2
B1
B0
WRITE ADDRESS
(hex)
READ ADDRESS
(hex)
GNDVID
1
0
01010
R/W
94h
95h
VVID
1
0
01011
R/W
96h
97h
SCL
10
01100
R/W
98h
99h
SDA
10
01101
R/W
9Ah
9Bh
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