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參數(shù)資料
| 型號： | MAX9602EUG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR HS 24-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 通用 |
| 元件數(shù)： | 4 |
| 輸出類型： | 補(bǔ)充型，差分，PECL |
| 電壓 - 輸入偏移（最小值）： | 5mV @ -5.2V，5V |
| 電流 - 輸入偏壓（最小值）： | 6µA @ -5.2V，5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 39mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 70dB CMRR，65dB PSRR |
| 傳輸延遲（最大）： | 0.5ns |
| 磁滯： | 30mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS_ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL = 5pF,
GND = 0V, RL = 50
to -2V (MAX9600), VCCO_ = 5V, RL = 50 to 3V (MAX9601/MAX9602), TA = TMIN to TMAX. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tracking Frequency Toggle Rate
fMAX
VOUT = 550mVP-P, input overdrive = 100mV
4
Gbps
Minimum Pulse Width
tPW
VOUT = 550mVP-P, input overdrive = 100mV
250
ps
Propagation Delay
tPD-, tPD+ Input overdrive = 100mV, Figure 1, (Note 3)
500
700
ps
Propagation Delay Tempco
TCtPD
0.5
ps/
°C
Propagation Delay Skew
tPDSKEW
Input overdrive = 100mV (Note 4)
10
ps
Propagation Delay Match
Input overdrive = 100mV (Note 5)
40
ps
10mV to 100mV
15
Propagation Delay Dispersion
Overdrive
100mV to 2V
40
ps
Propagation Delay Dispersion
Common-Mode Voltage
(VEE + 3V)
≤ VCM ≤ (VCC - 2V)
10
Propagation Delay Dispersion
Input Slew Rate
0.2V/ns to 10V/ns
40
Propagation Delay Dispersion
Duty Cycle
10% to 90% at 250MHz
30
Propagation Delay Dispersion
Pulse Width
VIN = 1VP-P
input
overdrive =
100mV
350ps to 1ns
20
ps
Unit-to-Unit Propagation Delay
Match
Input overdrive = 100mV
50
ps
Output Jitter
VIN = 2VP-P; 50MHz
300
fs
Input Capacitance
CIN
IN_+ or IN_, with respect to GND
2
pF
Latch Setup Time
tLS
Figure 1, (Notes 3, 6)
250
80
ps
Latch Hold Time
tLH
Figure 1, (Notes 3, 6)
300
85
ps
Minimum Pulse Width
tLPW
Figure 1
250
ps
Latch to Output Delay
tLPD
Figure 1
200
ps
Rise Time and Fall Time
tR, tF
20% to 80%, Figure 1
200
ps
Note 1: All devices are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Does not include output state current in Q_, Q_.
Note 3: Guaranteed by design.
Note 4: Propagation delay skew (tPDSKEW) is for a single channel and is the difference between the propagation delay to the high-
to-low output transition vs. the low-to-high output transition.
Note 5: Propagation delay match is the difference of tPD- or tPD+ of one channel to the tPD- or tPD+ of another channel of the same device.
Note 6: Latch setup and hold-timing specifications are for a differentially driven latch signal.
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