參數(shù)資料
型號(hào): MAX9648AXK+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/11頁(yè)
文件大?。?/td> 0K
描述: IC COMPARATOR GP SGL SC70-5
標(biāo)準(zhǔn)包裝: 2,500
類型: 通用
元件數(shù): 1
輸出類型: 開路漏極
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
電壓 - 輸入偏移(最小值): 7mV @ 5V
電流 - 輸入偏壓(最小值): 0.25µA @ 5V
電流 - 輸出(標(biāo)準(zhǔn)): 35mA @ 5V
電流 - 靜態(tài)(最大值): 120µA
CMRR, PSRR(標(biāo)準(zhǔn)): 90dB PSRR
傳輸延遲(最大): 110ns
工作溫度: -40°C ~ 125°C
封裝/外殼: *
安裝類型: *
包裝: *
MAX9647/MAX9648
General-Purpose, Low-Voltage,
Tiny Pack Comparators
9
Maxim Integrated
Additional hysteresis can be generated with two resis-
tors using positive feedback (Figure 2). Use the following
procedure to calculate resistor values:
1) Find output voltage when output is high:
VOUT(HIGH) = VDD - ILOAD x RL
2) Find the trip points of the comparator using these
formulas:
VTH = VREF + ((VOUT(HIGH) - VREF)R2)/(R1 + R2)
VTL = VREF(1 - (R2/(R1 + R2)))
where VTH is the threshold voltage at which the compara-
tor switches its output from high to low as VIN rises above
the trip point, and VTL is the threshold voltage at which
the comparator switches its output from low to high as
VIN drops below the trip point.
3) The hysteresis band is:
VHYST = VTH - VTL = VDD(R2/(R1 + R2))
In this example, let VDD = 5V, VREF = 2.5V, ILOAD =
50nA, and RL = 5.1kI.
VOUT(HIGH) = 5.0V - (50 x 10-9 x 5.1 x 103I) ≈ 5.0V
VTH = 2.5 + 2.5(R2/(R1 + R2))
VTL = 2.5(1 - (R2/(R1 + R2)))
Select R2. In this example, choose 1kI.
Select VHYST. In this example, choose 50mV.
Solve for R1.
VHYST = VOUT(HIGH)(R2/(R1 + R2))V
0.050V = 5(1000/(R1 + 1000))V
where R1
≈ 100kI, VTH = 2.525V, and VTL = 2.475V
Choose R1 and R2 to be large enough as not to exceed
the amount of current the reference can supply.
The source current required is VREF/(R1 + R2).
The sink current is (VOUT(HIGH) - VREF) x (R1 + R2).
Choose RL to be large enough to avoid drawing excess
current, yet small enough to supply the necessary cur-
rent to drive the load. RL should be between 1kI and
10kI. Choose R1 to be much larger than RL to avoid
lowering VOUT(HIGH) ir raising VOUT(LOW).
Board Layout and Bypassing
Use 0.1FF bypass capacitors from VDD to VSS. To maxi-
mize performance, minimize stray inductance by putting
this capacitor close to the VDD pin and reducing trace
lengths. For slow moving input signals (rise time > 1ms),
use a 1nF capacitor between IN+ and IN- to reduce high
frequency noise.
Figure 1. Threshold Hysteresis Band (Not to Scale)
Figure 2. Adding Hysteresis with External Resistors
IN+
THRESHOLDS
IN-
VHYST
VTL
VTH
HYSTERESIS
BAND
OUT
IN+
OUT
RL
R1
R2
VREF
VIN
VDD
VOUT
VDD
VSS
IN-
MAX9647
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