參數(shù)資料
型號(hào): MAX9675EVKIT+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 6/27頁(yè)
文件大小: 0K
描述: KIT EVAL FOR MAX9675
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,交叉點(diǎn)開(kāi)關(guān)/多路復(fù)用器
嵌入式:
已用 IC / 零件: MAX9675
主要屬性: 16 x 16 視頻交叉點(diǎn)開(kāi)關(guān)
次要屬性: 圖形用戶界面,USB 接口
已供物品: 板,纜線,CD
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
14
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 3, 5, 7, 9, 11, 13, 15,
17, 19, 21, 23
IN4–IN15
Buffered Analog Inputs
2, 4, 6, 8, 10, 12, 14, 16,
45, 46, 82, 83, 84, 91,
93, 95, 97
AGND
Analog Ground
18, 20, 22, 24
A3–A0
Address Programming Inputs. Connect to DGND or VDD to select the address for
Individual Output Address Mode (see Table 3).
25, 47, 51, 55, 59, 63,
67, 71, 75, 81
VCC
Positive Analog Supply. Bypass each pin with a 0.1F capacitor to AGND. Connect
a single 10F capacitor from one VCC pin to AGND.
26, 27, 38–44, 76, 77,
85–89, 99, 100
N.C.
No Connection. Not internally connected. Connect to AGND.
28
DOUT
Serial-Data Output. In Complete Matrix Mode, data is clocked through the 96-bit
Matrix Control shift register. In Individual Output Address Mode, data at DIN
passes directly to DOUT.
29
DGND
Digital Ground
30
AOUT
Address Recognition Output. AOUT drives low after successful chip address
recognition.
31
SCLK
Serial-Clock Input
32
CE
Clock Enable Input. Drive low to enable the serial data interface.
33
MODE
Serial Interface Mode Select Input. Drive high for Complete Matrix Mode (Mode 1)
or drive low for Individual Output Address Mode (Mode 0).
34
RESET
Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset. All
matrix settings are set to power up defaults and all analog outputs are disabled.
Additional power-on-reset delay may be set by connecting a small capacitor from
RESET to DGND.
35
UPDATE
Update Input. Drive UPDATE low to transfer data from mode registers to the switch
matrix.
36
DIN
Serial-Data Input. Data is clocked in on the falling edge of SCLK.
37
VDD
Digital Logic Supply. Bypass VDD with a 0.1F capacitor to DGND.
48, 50, 52, 54, 56, 58,
60, 62, 64, 66, 68, 70,
72, 74, 78, 80
OUT15–OUT0
Buffered Analog Outputs. Gain is individually programmable for AV = +1V/V or AV
= +2V/V through the serial interface. Outputs may be individually disabled (high
impedance). On power-up, or assertion of RESET, all outputs are disabled.
49, 53, 57, 61, 65, 69,
73, 79, 98
VEE
Negative Analog Supply. Bypass each pin with a 0.1F capacitor to AGND.
Connect a single 10F capacitor from one VEE pin to AGND.
90, 92, 94, 96
IN0–IN3
Buffered Analog Inputs
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