參數(shù)資料
型號: MAX97003EWP+T
廠商: Maxim Integrated Products
文件頁數(shù): 33/48頁
文件大?。?/td> 0K
描述: IC AUDIO SUBSYSTEM LN 20WLP
標(biāo)準(zhǔn)包裝: 2,500
類型: D 類;H 類
輸出類型: 1-通道(單聲道)或 2-通道(立體聲)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 1W x 2 @ 8 歐姆
電源電壓: 2.7 V ~ 5.5 V
特點(diǎn): 消除爆音,差分輸入,關(guān)閉
安裝類型: *
供應(yīng)商設(shè)備封裝: *
封裝/外殼: *
包裝: *
Maxim Integrated Products 39
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Table 11. Advanced Configuration Register
Advanced Configuration
The IC includes several advanced configurations related to automatic volume changes initiated by the DRC, expander,
and distortion limiter. In addition, settings for the Class D speaker modulation scheme and headphone charge pump
are configured in register 0x11.
REGISTER
BIT
NAME
DESCRIPTION
0x11
7
VS2EN
Enhanced Volume Smoothing. During volume slewing, the controller waits for each step
in the ramp to be applied before executing the next step. When zero-crossing detection
is enabled, this prevents large steps in the output volume when no zero-crossings are
detected.
0 = Disabled
1 = Enabled
6
SLEW
Volume Slewing. Determines whether volume slewing is used on all volume control
changes to reduce clicks and pops. When enabled, volume changes cause the IC to
ramp through intermediate volume settings whenever a change to the volume is made. If
ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew time depends on
the input signal frequency. This bit also activates soft-start at power-on and soft-stop at
power-off.
0 = Enabled
1 = Disabled
5
ZCD
Zero-Crossing Detection. Determines whether zero-crossing detection is used on all
volume control changes to reduce clicks and pops. Disabling zero-crossing detection
allows volume changes to occur immediately. Zero-crossing detection times out at
100ms.
0 = Enabled
1 = Disabled
3
FFM
Fixed Class D Frequency Enable
0 = Spread-spectrum modulation
1 = Fixed-frequency modulation
1
CPSEL
Charge-Pump Output Select. Works with FIXED to set QVDD or QVDD/2 outputs on
CPVDD and CPVSS. Ignored when FIXED = 0.
0 = QVDD on CPVDD/CPVSS
1 = QVDD/2 on CPVDD/CPVSS
0
FIXED
Class H Mode. When enabled, this bit forces the charge pump to generate static power
rails for CPVDD and CPVSS, instead of dynamically adjusting them based on output
signal level.
0 = Class H mode
1 = Fixed supply mode
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