參數(shù)資料
型號(hào): MAX975ESA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 5/17頁(yè)
文件大?。?/td> 0K
描述: IC COMPARATOR SNGL 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 通用
元件數(shù): 1
輸出類(lèi)型: CMOS,滿(mǎn)擺幅,TTL
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5.25 V
電壓 - 輸入偏移(最小值): 2mV @ 5V
電流 - 輸入偏壓(最小值): 0.1µA @ 5.25V
電流 - 靜態(tài)(最大值): 500µA
CMRR, PSRR(標(biāo)準(zhǔn)): 90dB CMRR,90dB PSRR
傳輸延遲(最大): 820ns
磁滯: 4mV
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類(lèi)型: 表面貼裝
包裝: 帶卷 (TR)
__________Applications Information
Powering Circuitry with STAT
STAT’s function is to indicate the comparator’s operat-
ing mode. When STAT is low, the comparator is in high-
speed mode and will meet the guaranteed propagation
delay. When STAT is high, the comparator is in auto-
standby mode, in low-power mode, or in transition to
high-speed mode. An additional feature of this pin is
that it can source 3mA of current. When STAT is high,
additional circuitry can be powered. This circuitry can
be automatically powered up or powered down,
depending on the input signal or lack of input signal
received by the MAX975/MAX977.
STO_ Considerations
The charge currents for the capacitor connected to
STO_ are on the order of 100nA. This necessitates cau-
tion in capacitor type selection and board layout.
Capacitor leakage currents must be less than 1nA to
prevent timing errors. Ceramic capacitors are available
in values up to 1F, and are an excellent choice for this
application. If a larger capacitance value is needed,
use parallel ceramic capacitors to get the required
capacitance. Aluminum and tantalum electrolytic
capacitors are not recommended due to their higher
leakage currents.
Board layout can create timing errors due to parasitic
effects. Make the STO_ traces as short as possible to
reduce capacitance and coupling effects. When driving
STO_ to disable auto-standby mode, use standard
CMOS logic isolated with a low-leakage (<1nA) diode,
such as National’s FJT1100 (Figure 3). 15nA leakage
typically results in 10% error.
The MAX977 has separate timing inputs (STOA and
STOB). These pins must have separate capacitors. The
timing circuits will not operate correctly if a single
capacitor is used with STOA and STOB connected
together.
The relationship between the timeout period and the
STO_ capacitor is tASB = 10 x CSTO_
s, where CSTO_
is in pF. This equation is for larger capacitance values,
and does not take into account variations due to board
capacitance and board leakage. If less than 1ms is
desired, subtract the ~3pF STO_ parasitic capacitance
from the calculated value.
Circuit Layout and Bypassing
The MAX975/MAX977’s high gain bandwidth requires
design precautions to realize the comparator’s full high-
speed capability. The following precautions are recom-
mended:
1) Use a printed circuit board with an unbroken, low-
inductance ground plane.
2) Place a decoupling capacitor (a 0.1F ceramic
capacitor is a good choice) as close to VCC as pos-
sible.
3) Keep lead lengths short on the inputs and outputs, to
avoid unwanted parasitic feedback around the com-
parators.
4) Solder the devices directly to the printed circuit
board instead of using a socket.
5) Minimize input impedance.
6) For slowly varying inputs, use a small capacitor
(~1000pF) across the inputs to improve stability.
IR Receiver
Figure 4 shows an application using the MAX975 as an
infrared receiver. The infrared photodiode creates a
current relative to the amount of infrared light present.
This current creates a voltage across RD. When this
voltage level crosses the voltage applied by the voltage
divider to the inverting input, the output transitions. If
the photodiode is not receiving enough signal to cause
transitions on the MAX975’s output, STAT is used as a
loss-of-signal indicator. R3 adds additional hysteresis
for noise immunity.
MAX975/MAX977
Single/Dual, +3V/+5V Dual-Speed
Comparators with Auto-Standby
______________________________________________________________________________________
13
STO_
CMOS
LOGIC
Figure 3. Driving STO
_ with CMOS Logic
GND
STAT
VCC
RD
R1
R2
R3
OUT
LOSS OF SIGNAL
MAX975
VCC
Figure 4. IR Receiver
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