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| 型號(hào)： | MAX9888EVKIT+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/115頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVALUATION FOR MAX9888 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | DirectDrive®, FLEXSOUND™ |
| 相關(guān)產(chǎn)品： | MAX9888EWY+T-ND - IC CODEC AUDIO FLEXSOUND 63WLP |
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Stereo Audio CODEC
with FlexSound Technology
MAX9888
103
Table 37. Status and Interrupt Registers
Device Status
The IC uses register 0x00 and IRQ to report the status of
various device functions. The status register bits are set
when their respective events occur, and cleared upon
reading the register. Device status can be determined
either by poling register 0x00 or configuring the IRQ to
pull low when specific events occur. IRQ is an open-
drain output that requires a pullup resistor for proper
operation. Register 0x0F determines which bits in the
status register trigger IRQ to pull low.
REGISTER
BIT
NAME
DESCRIPTION
0x00
(Read Only)
7
CLD
Full Scale
0 = All digital signals are less than full scale.
1 = The DAC or ADC signal path has reached or exceeded full scale. This typically
indicates clipping.
6
SLD
Volume Slew Complete
SLD reports that any of the programmable-gain arrays or volume controllers has
completed slewing from a previous setting to a new programmed setting. If multiple
gain arrays or volume controllers are changed at the same time, the SLD flag is set
after the last volume slew completes. SLD also reports when the digital audio interface
soft-start or soft-stop process has completed. MCLK is required for proper SLD
operation.
0 = No volume slewing sequences have completed since the status register was last
read.
1 = Volume slewing complete.
5
ULK
Digital Audio Interface Unlocked
0 = Both digital audio interfaces are operating normally.
1 = Either digital audio interface is configured incorrectly or receiving invalid data.
1
JDET
Jack Configuration Change
JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack
Status bits are debounced before setting JDET. The debounce period is programmable
using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first
time power is applied to the IC. Read the status register following such an event to clear
JDET and allow for proper jack detection.
0 = No change in jack configuration.
1 = Jack configuration has changed.
0x0F
7
ICLD
Full-Scale Interrupt Enable
0 = Disabled
1 = Enabled
6
ISLD
Volume Slew Complete Interrupt Enable
0 = Disabled
1 = Enabled
5
IULK
Digital Audio Interface Unlocked Interrupt Enable
0 = Disabled
1 = Enabled
1
IJDET
Jack Configuration Change Interrupt Enable
0 = Disabled
1 = Enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9888EVKIT+ | 功能描述:音頻 IC 開(kāi)發(fā)工具 MAX9888 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| MAX9888EWY+T | 功能描述:接口—CODEC Stereo Audio CODEC RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| MAX9889EWO+T | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| MAX988ESA | 功能描述:校驗(yàn)器 IC Single uPower Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類(lèi)型: 通道數(shù)量: 輸出類(lèi)型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
| MAX988ESA+ | 功能描述:校驗(yàn)器 IC Single uPower Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類(lèi)型: 通道數(shù)量: 輸出類(lèi)型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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