參數(shù)資料
型號(hào): MAX9967BRCCQ+TD
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 19/30頁(yè)
文件大小: 0K
描述: IC DCL DUAL 500MBPS ATE 100TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ATE
邏輯類(lèi)型: 比較器, 驅(qū)動(dòng)器
電源電壓: -1.5 V ~ 6.5 V
位數(shù): 2
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
26
______________________________________________________________________________________
Serial Interface and Device Control
A CMOS-compatible serial interface controls the
MAX9967 modes (Figure 5). Control data flow into an 8-
bit shift register (MSB first) and are latched when CS is
taken high, as shown in Figure 6. Latches contain 6 con-
trol bits for each channel of the dual pin driver. Data
from the shift register are loaded to either or both of the
latches as determined by bits D6 and D7, and indicated
in Figure 5 and Table 5. The control bits, in conjunction
with external inputs DATA_ and RCV_, manage the fea-
tures of each channel, as shown in Tables 1 and 2. RST
sets LLEAK = 1 for both channels, forcing them into low-
leakage mode. All other bits are unaffected. At power-
up, hold RST low until VCC and VEE have stabilized.
Analog control input THR sets the threshold for the
input logic, allowing operation with CMOS logic as low
as 0.9V. Leaving THR unconnected results in a nominal
threshold of 1.25V from an internal reference, providing
compatibility with 2.5 to 3.3V logic.
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
D0
tCH
tCSS0
tOH
tCL
tCSS1
tCSH1
tCSWH
tDS
CS
Figure 6. Serial-Interface Timing
BIT
NAME
DESCRIPTION
D7
CH1
Channel 1 Write Enable. Set to 1 to update the control byte for channel 1. Set to 0 to make no changes to
channel 1.
D6
CH2
Channel 2 Write Enable. Set to 1 to update the control byte for channel 2. Set to 0 to make no changes to
channel 2.
D5
LLEAK
Low-Leakage Select. Set to 1 to put driver, load, and clamps into low-leakage mode. Comparators remain
active in low-leakage mode. Set to 0 for normal operation.
D4
TMSEL
Driver Termination Select. Set to 1 to force the driver output to the DTV_ voltage when RCV_ = 1 (term). Set to
0 to place the driver into high-impedance mode when RCV_ = 1 (high-Z). See Table 1.
D3
SC1
D2
SC0
Driver Slew-Rate Select. SC1 and SC0 set the driver slew rate. See Table 2.
D1
LDDIS
Load Disable. Set LDDIS to 1 to disable the load. Set to 0 for normal operation. See Table 4.
D0
LDCAL
Load Calibrate. Overrides LDEN to enable load. Set LDCAL to 1 to enable load. Set LDCAL to 0 for normal
operation. See Table 4.
Table 5. Shift-Register Functions
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