參數(shù)資料
型號(hào): MAXQ612J-0000+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 12 MHz, RISC MICROCONTROLLER, QCC44
封裝: ROHS COMPLIANT, TQFN-44
文件頁數(shù): 24/35頁
文件大?。?/td> 1430K
代理商: MAXQ612J-0000+
16-Bit Microcontrollers with
Infrared Module and Optional USB
MAXQ612/MAXQ622
30 _____________________________________________________________________________________
nanopower ring-oscillator cycles. If VDD > VRST during
detection, VDD is monitored for an additional nanopower
ring-oscillator period. If VDD remains above VRST for
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the CPU
exits the reset state in less than 20 crystal cycles after
the reset source is removed.
Table 5. Power-Fail Detection States During Normal Operation
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMMENTS
A
On
Off
VDD < VPOR.
B
On
VPOR < VDD < VRST.
Crystal warmup time, tXTAL_RDY.
CPU held in reset.
C
On
VDD > VRST.
CPU normal operation.
D
On
Power drop too short.
Power-fail not detected.
E
On
VRST < VDD < VPFW.
PFI is set when VRST < VDD < VPFW and
maintains this state for at least tPFW, at
which time a power-fail interrupt is gener-
ated (if enabled).
CPU continues normal operation.
F
On
(Periodically)
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
G
On
VDD > VRST.
Crystal warmup time, tXTAL_RDY.
CPU resumes normal operation from
8000h.
H
On
(Periodically)
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
I
Off
VDD < VPOR.
Device held in reset. No operation allowed.
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