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參數(shù)資料
| 型號(hào)： | MAXQ622G-0000+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 12 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | ROHS COMPLIANT, LQFP-64 |
| 文件頁數(shù)： | 2/35頁 |
| 文件大?。?/td> | 1430K |
| 代理商： | MAXQ622G-0000+ |
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16-Bit Microcontrollers with
Infrared Module and Optional USB
MAXQ612/MAXQ622
10 _____________________________________________________________________________________
Figure 1. Series Resistors (RS) for Protecting Against High-Voltage Spikes
Note 15: For USB operation, both VDD and VBUS must be connected.
Note 16: FRCVDD is the force VDD power-supply bit (PWCN.10). When FRCVDD = 1, VDDB power switching is disabled, and VDD
is always used as the core 3V power supply.
Note 17: The ESD protection scheme is in production on existing parts. The 1FF capacitor on VBUS is intended to protect that
pin from ESD damage (rather than DP or DM) since it is externally exposed. The ESD test uses 150pF charged to 15kV
applied to the 1FF capacitor creating a delta V of approximately 2.25V and limiting the voltage on VBUS.
Note 18: Devices that use nonstandard supply voltages that do not conform to the intended I2C bus system levels must relate their
input levels to the voltage to which the pullup resistors RP are connected.
Note 19: The maximum fall time, tF_I2C of 300ns for the SDA and SCL bus lines is longer than the specificed maximum tOF_I2C of
250ns for the output stages. This allows series protection resistors (RS) to be connected between the SDA/SCL pins and
the SDA/SCL bus lines as shown in I2C Bus Controller Timing without exceeding the maximum specified fall time.
Note 20: CB = Capacitance of one bus line in pF.
Note 21: All values referred to VIH_I2C(MIN) and VIL_I2C (MAX).
Note 22: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH_I2C(MIN) of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 23: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW_I2C) of the SCL signal.
Note 24: A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU:DAT R 250ns must
be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR_I2C(MAX) + tSU:DAT =
1000 + 250 = 1250ns (according to the standard-mode I2C specification) before the SCL line is released.
Note 25: AC electrical specifications are guaranteed by design and are not production tested.
Figure 2. I2C Bus Controller Timing Diagram
SDA
P0.3
SCL
P0.4
RS
I2C
DEVICE
RS
I2C
DEVICE
RP
VDD
MAXQ612
MAXQ622
SDA
SCL
S
SR
P
S
tF_I2C
tR_I2C
tLOW_I2C
tHIGH_I2C
tHD:STA
tSU:DAT
tSU:STA
tSU:STO
tBUF
tHD:DAT
NOTE: TIMING REFERENCED TO VIH_I2C(MIN) AND VIL_I2C(MAX).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAXQ622G-0000+ | 功能描述:16位微控制器 - MCU 16-Bit MCU w/Infrared Module RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MAXQ622G-UEI+ | 制造商:Maxim Integrated Products 功能描述:MAXQ622 BLANK 64 LQFP FW SCRT UEI - Rail/Tube |
| MAXQ622-KIT# | 功能描述:開發(fā)板和工具包 - 其他處理器 MAXQ622 Eval Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MAXQ622X-0000+ | 功能描述:16位微控制器 - MCU 16-Bit MCU w/Infrared Module RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MAXQ622X-UEI+ | 制造商:Maxim Integrated Products 功能描述:MAXQ622 BLANK WLF FW SCRT UEI - Gel-pak, waffle pack, wafer, diced wafer on film |
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