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MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
36
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Interrupts
Multiple interrupt sources are available for quick
response to internal and external events. The MAXQ
architecture uses a single interrupt vector (IV), single
interrupt-service routine (ISR) design. For maximum
flexibility, interrupts can be enabled globally, individual-
ly, or by module. When an interrupt condition occurs,
its individual flag is set, even if the interrupt source is
disabled at the local, module, or global level. Interrupt
flags must be cleared within the user-interrupt routine
to avoid repeated false interrupts from the same
source. Application software must ensure a delay
between the write to the flag and the RETI instruction to
allow time for the interrupt hardware to remove the
internal interrupt condition. Asynchronous interrupt
flags require a one-instruction delay and synchronous
interrupt flags require a two-instruction delay.
When an enabled interrupt is detected, software jumps
to a user-programmable interrupt vector location. The
IV register defaults to 0000h on reset or power-up, so if
it is not changed to a different address, the user pro-
gram must determine whether a jump to 0000h came
from a reset or interrupt source.
Once software control has been transferred to the ISR,
the interrupt identification register (IIR) can be used to
determine if a system register or peripheral register
was the source of the interrupt. The specified module
can then be interrogated for the specific interrupt
source and software can take appropriate action.
Because the interrupts are evaluated by user software,
the user can define a unique interrupt priority scheme
for each application. The following interrupt sources are
available.
Watchdog interrupt
External interrupts 0 to 7
Serial port 0 receive and transmit interrupts
Timer 0 low compare, low overflow, capture/compare,
and overflow interrupts
Timer 1 low compare, low overflow, capture/compare,
and overflow interrupts
Timer 2 low compare, low overflow, and overflow
interrupts
CAN0 receive and transmit interrupts and a change
in CAN0 status register interrupt
ADC data ready and overrun interrupts
Digital and I/O voltage brownout interrupts
High-frequency oscillator failure interrupt
Reset Sources
Several reset sources are provided for C control.
Although code execution is halted in the reset state, the
high-frequency oscillator and the internal RC oscillator
continue to oscillate. The high-frequency oscillator is
turned off by a POR, but not by other reset sources.
Internal resets such as the power-on and watchdog
resets assert the RESET output low.
Power-On Reset (POR)
An internal POR circuit enhances system reliability. This
circuit forces the device to perform a POR whenever a
rising voltage on DVDD climbs above the POR threshold
level of 2.7V. At this point the following events occur:
All registers and circuits enter their reset state
The POR flag (WDCN.POR) is set to indicate the
source of the reset
The internal RC oscillator becomes the clock source
Code execution begins at location 8000h
Watchdog Timer Reset
The watchdog timer functions are described in the
MAXQ7665/MAXQ7666 User’s Guide. Execution resumes
at location 8000h following a watchdog timer reset.