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MAXQ7667
16-Bit, RISC, Microcontroller-Based,
Ultrasonic Distance-Measuring System
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not externally forced low. An internal POR flag indicates
the source of a reset. Ramp up the DVDD supply at a
minimum rate of 60mV/ms to keep the device in POR
until DVDD fully settles.
Watchdog Timer
The primary function of the watchdog timer is to watch
for stalled or stuck software. The watchdog timer per-
forms a controlled system restart when the P fails to
write to the watchdog timer register before a selectable
timeout interval expires. The internal 13.5MHz RC oscil-
lator drives the MAXQ7667’s watchdog timer.
Figure 14 shows the watchdog timer functions as the
source of both the watchdog interrupt and watchdog
reset. The watchdog interrupt timeout period is pro-
grammable to 212, 215, 218, or 221 cycles of the RC
oscillator resulting in a nominal range of 273s to
139.8ms. The watchdog reset timeout period is a fixed
512 RC clock cycles (34s). When enabled, the watch-
dog generates an interrupt upon expiration; then, if not
reset within 512 RC clock cycles, the watchdog asserts
RESET low for eight RC clock cycles.
Hardware Multiplier/Accumulator
A hardware multiplier supports high-speed multiplica-
tions. The multiplier completes a 16-bit x 16-bit multipli-
cation in a single clock cycle and contains a 48-bit
accumulator. The multiplier is a peripheral that per-
forms seven different multiplication operations:
Unsigned 16-bit multiplication
Unsigned 16-bit multiplication and accumulation
Unsigned 16-bit multiplication and subtraction
Signed 16-bit multiplication
Signed 16-bit multiplication and negation
Signed 16-bit multiplication and accumulation
Signed 16-bit multiplication and subtraction
MAXQ Core Architecture
The MAXQ20 C is an accumulator-based Harvard
memory architecture. Fetch and execution operations
complete in one clock cycle without pipelining because
the instruction contains both the op code and data. The
C streamlines 16 million instructions per second
(MIPS). Integrated 16-level hardware stack enables fast
subroutine calling and task switching. Manipulate data
quickly and efficiently with three internal data pointers.
Multiple data pointers allow more than one function to
access data memory without having to save and
restore data pointers each time. The data pointers auto-
matically increment or decrement following an opera-
tion, eliminating the need for software intervention.
Instruction Set
The instruction set consists of a total of 33 fixed-length
16-bit instructions that operate on registers and memo-
ry locations. The highly orthogonal instruction set allows
arithmetic and logical operations to use any register
along with the accumulator. System registers control
functionality common to all MAXQ Cs, while peripheral
registers control peripherals and functions specific to
the MAXQ7667. All registers are subdivided into regis-
ter modules.
The architecture is transport-triggered. Writes or reads
from certain register locations potentially have side
effects. These side effects form the basis for the higher
level op codes defined by the assembler, such as
ADDC, OR, JUMP, etc. The op codes are implemented
as MOVE instructions between system registers. The
assembler handles all the instruction encoding.
Memory Organization
In addition to the internal register space, the device
incorporates several memory areas:
16Kwords of flash memory for program storage
2Kword of SRAM for storage of temporary variables
4Kwords utility ROM
16-level, 16-bit-wide hardware stack for storage of
program return addresses and general-purpose use
Use the internal memory-management unit (MMU) to
map data memory space into a predefined program
memory segment for code execution from data memory.
Use the MMU to map program memory space as data
space for access to constant data stored in program
EWDI
WD0
RWT
WD1
RC CLOCK
(13.5MHz)
INTERRUPT
WTRF
RESET
WDIF
TIMEOUT
TIME
212
DIV 212
DIV 23
215 218 221
EWT
RESET
Figure 14. Watchdog Functional Diagram