參數(shù)資料
型號(hào): MB15E05
廠商: Fujitsu Limited
英文描述: Serial Input PLL Frequency Synthesizer(串行輸入PLL頻率合成器)
中文描述: 串行輸入鎖相環(huán)頻率合成器(串行輸入鎖相環(huán)頻率合成器)
文件頁數(shù): 7/20頁
文件大?。?/td> 158K
代理商: MB15E05
7
MB15E05
I
FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
VCO
= [(M x N) + A] x f
OSC
÷
R (A < N)
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0
A
127)
f
OSC
: Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M
: Preset divide ratio of modules prescaler (64 or 128)
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Shift Register Configuration
Control bit (CNT)
Destination of serial data
H
17 bit latch (for the programmable reference divider)
L
18 bit latch (for the programmable divider)
Programmable Reference Counter
C
N
T
1
2
R
2
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
R
9
9
R
10
10
R
11
11
R
12
12
R
13
13
R
14
14
SW
15
FC
16
LDS
17
LSB
MSB
Data Flow
R
1
R
3
18
CNT
R1 to R14 : Divide ratio setting bit for the programmable reference counter (5 to 16,383)
SW
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
FC
: Phase control bit for the phase comparator
LDS
: LD/fout signal select bit
: Control bit
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
Note
:
Start data input with MSB first
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