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參數(shù)資料
| 型號(hào)： | MB15E06SRPV1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Single Serial Input PLL Frequency Synthesizer On-chip 3.0 GHz Prescaler |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3000 MHz, PBCC16 |
| 封裝： | PLASTIC, BCC-16 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 128K |
| 代理商： | MB15E06SRPV1 |
MB15E06SR
8
I
FUNCTIONAL DESCRIPTION
1.
Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
VCO
= [(P
×
N) + A]
×
f
OSC
÷
R (A < N)
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0
≤
A
≤
127)
f
OSC
: Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
P
: Preset divide ratio of modulus prescaler (64 or 128)
2.
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
(1) Shift Register Configuration
Control bit (CNT)
Destination of serial data
H
For the programmable reference divider
L
For the programmable divider
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CNT
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 SW
FC
LDS
Programmable Reference Counter
MSB
Data Flow
CNT
R1 to R14
SW
FC
LDS
: Control bit
: Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
: Phase control bit for the phase comparator
: LD/f
OUT
signal select bit
[Table 1]
[Table 5]
[Table 7]
[Table 6]
Note: Start data input with MSB first.
LSB
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