- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377879 > MB15F76ULPVA (FUJITSU LTD) Dual Serial Input PLL Frequency Synthesizer PDF資料下載
參數(shù)資料
| 型號： | MB15F76ULPVA |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 6000 MHz, PBCC20 |
| 封裝： | PLASTIC, BCC-20 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 155K |
| 代理商： | MB15F76ULPVA |
MB15F76UL
8
I
FUNCTIONAL DESCRIPTION
1.
Pulse swallow function
f
VCO
=
[ (P
×
N)
+
A]
×
4
×
f
OSC
÷
R
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
P
: Preset divide ratio of dual modulus prescaler (4 or 8 for IF-PLL, 16 or 32 for RF-PLL)
N
: Preset divide ratio of binary 13-bit programmable counter (3 to 8,191)
A
: Preset divide ratio of binary 5-bit swallow counter (0
≤
A
≤
31, A < N)
f
OSC
: Reference oscillation frequency (OSC
IN
input frequency)
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2.
Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-
PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
(1)
Shift Register Configuration
The programmable
reference counter
for the IF-PLL
The programmable
reference counter
for the RF-PLL
The programmable
counter and the swallow
counter for the IF-PLL
The programmable
counter and the swallow
counter for the RF-PLL
CN1
0
1
0
1
CN2
0
0
1
1
Programmable Reference Counter
CS
R1 to R14
T1, 2
CN1, 2
X
: Charge pump current select bit
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)
: LD/fout output setting bit
: Control bit
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
18
19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
X
X
X
(LSB)
(MSB)
Data Flow
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB15F76UV | ASSP Dual Serial Input PLL Frequency Synthesizer(Small Package) |
| MB15F78SP | Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPFT | Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPV | Dual Serial Input PLL Frequency Synthesizer |
| MB15F78UL | Dual Serial Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F76UV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:ASSP Dual Serial Input PLL Frequency Synthesizer(Small Package) |
| MB15F78SP | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F78UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。