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參數(shù)資料
| 型號： | MB15F78ULPFT |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大小： | 160K |
| 代理商： | MB15F78ULPFT |
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MB15F78UL
3
I
PIN DESCRIPTION
Pin no.
Pin name
I/O
Descriptions
TSSOP
BCC
1
19
OSC
IN
I
The programmable reference divider input pin. TCXO should be connected
with an AC coupling capacitor.
2
20
GND
Ground pin for OSC input buffer and the shift register circuit.
3
1
fin
TX
I
Prescaler input pin for the TX-PLL.
Connection to an external VCO should be via AC coupling.
4
2
Xfin
TX
I
Prescaler complimentary input pin for the TX-PLL section.
This pin should be grounded via a capacitor.
5
3
GND
TX
Ground pin for the TX-PLL section.
6
4
V
CCTX
Power supply voltage input pin for the TX-PLL section (except for the charge
pump circuit) , the oscillator input buffer and the shift register.
7
5
PS
TX
I
Power saving mode control pin for the TX-PLL section. This pin must be set
at “L” when the power supply is started up. (Open is prohibited.)
PS
TX
=
“H” ; Normal mode/PS
TX
=
“L” ; Power saving mode
Power supply voltage input pin for the TX-PLL charge pump.
8
6
Vp
TX
O
9
7
D
OTX
Charge pump output pin for the TX-PLL section.
10
8
LD/fout
O
Lock detect signal output (LD) /phase comparator monitoring
output (fout) .The output signal is selected by LDS bit in the serial data.
LDS bit
=
“H” ; outputs fout signal/LDS bit
=
“L” ; outputs LD signal
Charge pump output pin for the RX-PLL section.
11
9
D
ORX
O
12
10
Vp
RX
Power supply voltage input pin for the RX-PLL charge pump.
13
11
PS
RX
I
Power saving mode control pin for the RX-PLL section. This pin must be set
at “L” when the power supply is started up. (Open is prohibited.)
PS
RX
=
“H” ; Normal mode/PS
RX
=
“L” ; Power saving mode
Power supply voltage input pin for the RX-PLL section (except for the charge
pump circuit)
14
12
V
CCRX
15
13
GND
RX
Ground pin for the RX-PLL section
16
14
Xfin
RX
I
Prescaler complimentary input pin for the RX-PLL section.
This pin should be grounded via a capacitor.
17
15
fin
RX
I
Prescaler input pin for the RX-PLL.
Connection to an external VCO should be via AC coupling.
18
16
LE
I
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in a serial data.
19
17
Data
I
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (TX-ref. counter, TX-prog.
counter, RX-ref.counter, RX-prog.counter) according to the control bit in
a serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with a schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB15F78ULPVA | Dual Serial Input PLL Frequency Synthesizer |
| MB15F83UL | Fractional-N PLL Frequency Synthesizer |
| MB15F83ULPFT | Fractional-N PLL Frequency Synthesizer |
| MB15F83ULPVA | Fractional-N PLL Frequency Synthesizer |
| MB15F88UL | Fractional-N PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F78ULPFT-G-BND-EFE1 | 功能描述:IC SYNTHESIZR PLL DL INP 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| MB15F78ULPVA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F83UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Fractional-N PLL Frequency Synthesizer |
| MB15F83ULPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Fractional-N PLL Frequency Synthesizer |
| MB15F83ULPVA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Fractional-N PLL Frequency Synthesizer |
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