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參數(shù)資料
| 型號： | MB15U10 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Serial Input PLL Frequency Synthesizer(串行輸入PLL頻率合成器) |
| 中文描述： | 串行輸入鎖相環(huán)頻率合成器（串行輸入鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 171K |
| 代理商： | MB15U10 |
7
MB15U10
I
FUNCTIONAL DESCRIPTIONS
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider, program-
mable divider (PLL1) and programmable divider (PLL2) separately by means of address setting.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high, stored
data is latched.
a) Serial data input format
Note: Start data input with MSB first.
Auxiliary bit for test (no need at ordinary use)
Data setting
Address
(MSB)
(LSB)
Direction of data input
MA0 to 16 : Divide ratio setting bits of the main counter (PLL1)
MB0 to 16 : Divide ratio setting bits of the main counter (PLL2)
R0 to 11
: Divide ratio setting bits of the reference counter
SR
: Divide ratio select bit of reference frequency (PLL1 and PLL2)
P0 to 3
: Setting bits of P0 to P3 output pins
OLA, B
: Select bits of P0/LD pin output
CR1, 2
: Select bits of charge pump output current
PS1, 2
: Power saving mode control bits
TS
: Test bits (Set ”0” at ordinary use.)
X
: Dummy bits (Set ”0” or ”1”.)
0
: Set ”0”
[ See Table 1 ]
[ See Table 2 ]
[ See Table 3 ]
[ See Table 4 ]
[ See Table 5 ]
[ See Table 6 ]
[ See Table 7 ]
[ See Table 8 ]
[ See Table 9 ]
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
M
A
0
M
A
M
A
1
0
0
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
M
B
0
M
B
M
B
1
1
0
0
0
0
0
0
T
S
S
R
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
0
0
0
1
0
1
X
P
0
O
L
O
L
C
R
C
R
X
X
P
S
P
S
P
3
P
2
P
1
X
X
0
X
X
0
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
19
20
21
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| MB15U10PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz Prescaler |
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