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參數(shù)資料
| 型號： | MB15U10PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | USER CABLE WITH AUDIO 1 FT |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20 |
| 封裝： | PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 350K |
| 代理商： | MB15U10PFV |
8
MB15U10
b) Data setting description
Note:
Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071)
Note:
Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071)
Note:
Divide ratios less than 6 are prohibited. (Divide ratio = 6 to 4,095)
Note: R = Programmed value with R0 to R11 bits
Table 1 : MA0 to MA16 : Divide ratio of the binary 17-bit main counter (PLL1)
Divide Ratio
(MA)
M
A
16
M
A
15
M
A
14
M
A
13
M
A
12
M
A
11
M
A
10
M
A
9
M
A
8
M
A
7
M
A
6
M
A
5
M
A
4
M
A
3
M
A
2
M
A
1
M
A
0
1024
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1025
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
Table 2 : MB0 to MB16 : Divide ratio of the binary 17-bit main counter (PLL2)
Divide Ratio
(MB)
M
B
16
M
B
15
M
B
14
M
B
13
M
B
12
M
B
11
M
B
10
M
B
9
M
B
8
M
B
7
M
B
6
M
B
5
M
B
4
M
B
3
M
B
2
M
B
1
M
B
0
1024
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1025
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
Table 3 : R0 to R11 : Divide ratio of the binary 12-bit reference counter
Divide Ratio
(R)
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
6
0
0
0
0
0
0
0
0
0
1
1
0
7
0
0
0
0
0
0
0
0
0
1
1
1
Table 4 : Divide ratio select bit of reference frequency (PLL1 and PLL2)
SR
Divide ratio of reference
frequency (PLL1)
Divide ratio of reference
frequency (PLL2)
0
R
R
1
R
2R
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