參數(shù)資料
型號: MB2146-301A
廠商: Fujitsu Limited
英文描述: 8-bit Proprietary Microcontrollers
中文描述: 8位微控制器專有
文件頁數(shù): 53/69頁
文件大?。?/td> 832K
代理商: MB2146-301A
MB95100B Series
53
Sampling at the falling edge of sampling clock*
1
and prohibited serial clock delay*
2
(ESCR register : SCES bit
=
1, ECCR register : SCDE bit
=
0)
(V
CC
=
3.3 V, AV
SS
=
V
SS
=
0.0 V, T
A
=
40
°
C to
+
85
°
C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for t
MCLK
.
Parameter
Sym-
bol
Pin name
Conditions
Value
Unit
Min
Max
+
95
Serial clock cycle time
SCK
↑→
SOT delay time
Valid SIN
SCK
SCK
↓→
valid SIN hold time
Serial clock “H” pulse width
t
SCYC
SCK
Internal clock
operation output pin :
C
L
=
80 pF
+
1 TTL.
5 t
MCLK
*
3
95
t
MCLK
*
3
+
190
0
3 t
MCLK
*
3
t
R
t
MCLK
*
3
+
95
190
t
MCLK
*
3
+
95
ns
t
SHOVI
SCK, SOT
ns
t
IVSLI
SCK, SIN
ns
t
SLIXI
SCK, SIN
ns
t
SHSL
SCK
External clock
operation output pin :
C
L
=
80 pF
+
1 TTL.
ns
Serial clock “L” pulse width
SCK
SOT delay time
Valid SIN
SCK
SCK
↓→
valid SIN hold time
SCK fall time
t
SLSH
SCK
ns
t
SHOVE
SCK, SOT
2 t
MCLK
*
3
+
95
10
ns
t
IVSLE
SCK, SIN
ns
t
SLIXE
SCK, SIN
ns
t
F
SCK
ns
SCK rise time
t
R
SCK
10
ns
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