參數(shù)資料
型號(hào): MB3821PFV
廠商: FUJITSU LTD
元件分類: 穩(wěn)壓器
英文描述: 2-ch DC/DC Converter IC With Synchronous Rectifier
中文描述: 0.5 A DUAL SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO24
封裝: PLASTIC, SSOP-24
文件頁數(shù): 16/24頁
文件大?。?/td> 273K
代理商: MB3821PFV
16
MB3821
I
METHOD OF SETTING TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT
PROTECTION CIRCUIT
The short detection comparator (SCP comparator) constantly compares the error amplifier output level to the
reference voltage.
While the switching regulator load conditions are stable on all channels, the short detection comparator output
remains at “H” level, transistor Q1 is on, and the CSCP terminal (pin 22) is held at input standby voltage (V
STB
: 50mV).
If the load conditions change rapidly due to a short-circuiting of load, causing the output voltage to drop, the output
from the short detection comparator goes to “L” level. This causes transistor Q1 to turn off and the external short
protection capacitor C
SCP
connected to the CSCP pin to charge at 1.0
μ
A.
Short Detection Time
t
SCP
(sec) : 0.7
×
C
SCP
(
μ
F)
When the capacitor C
SCP
is charged to the threshold voltage V
TH
: 0.7 V, the SR latch is set, and the external FET
is turned off (inactive interval is set to 100%). At this point, the SR latch input is closed and the CSCP terminal is
held at input latch voltage (V
I
: 50 mV).
+
+
1.26 V
Error
Amp.1
Error
Amp.2
22
C
SCP
CSCP
Q1
Q4
1
μ
A
+
2.1 V
UVLO
Power
ON/OFF
SCP Comp.
Q2
18
CTL
OUT2
2
OUT2
1
OUT1
2
OUT1
1
14
17
11
8
6
5
4
FB1
CS1
Cs1
IN1
1
μ
A
1
μ
A
bias
+
+
1.26 V
Q3
19
20
21
FB2
CS2
Cs2
IN2
Latch
S
R
bias
(2.5V)
Ref
Timer-latch short-circuit protection circuit
Output stage
Output stage
Output stage
Output stage
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