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參數(shù)資料
| 型號(hào)： | MB40568PF |
| 廠商： | FUJITSU LTD |
| 元件分類： | ADC |
| 英文描述： | A/D Converter (1-channel, 8-bit low-power model with built-in clamp circuit) |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SOP-24 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 175K |
| 代理商： | MB40568PF |
2
MB40568
I
PIN ASSIGNMENTS
I
PIN DESCRIPTIONS
(Continued)
Pin no.
Symbol
Function
DIP
SOP
1, 11
1, 11
D.GND
Ground pin
Should be connected to the analog system ground.
2 to 9
2 to 9
D
8
to D
1
Digital signal output pin
10
10
CLK
Clock input pin
12, 22
12, 24
A.GND
Ground pin
Should be connected to the analog system ground.
13, 21
13, 23
V
CCD
Power supply voltage input pin
Also functions as V
CCA
power supply, and should be in the same
voltage level as V
CCA
pin.
14, 20
14, 22
V
CCA
Power supply voltage input pin
Also functions as V
CCD
power supply, and should be in the same
voltage level as V
CCD
pin.
15
15
V
INC
Clamp circuit input pin
The clamp circuit is a diode-clamp type sync chip clamp circuit.
Should be shorted to ground if the clamp circuit is not used.
16
16
V
OUTC
Clamp circuit output pin
A capacitor of at least 1
μ
F should be connected between this pin
and the V
CLMP
pin.
Should be left open if the clamp circuit is not used.
D.GND
D
8
(LSB)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
(MSB)
CLK
D.GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
A.GND
V
CCD
V
CCA
V
RB
V
INA
V
CLMP
V
OUTC
V
INC
V
CCA
V
CCD
A.GND
(Top view)
(DIP-22P-M04)
(FPT-24P-M02)
D.GND
D
8
(LSB)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
(MSB)
CLK
D.GND
A.GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A.GND
V
CCD
V
CCA
V
RB
V
REF
V
RM
V
INA
V
CLMP
V
OUTC
V
INC
V
CCA
V
CCD
(Top view)
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