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參數(shù)資料
| 型號： | MB40C318PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | ADC |
| 英文描述： | 8-bit 140 MSPS A/D Converter |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 173K |
| 代理商： | MB40C318PFV |
6
MB40C318
I
RECOMMENDED OPERATING CONDITIONS
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Value
Typ.
3.30
5.00
3.30
—
—
—
2.00
—
Unit
Min.
3.00
4.75
3.00
V
RB
—
0.00
1.90
Max.
3.60
5.25
3.60
V
RT
3.00
—
2.10
—
Power supply voltage
AV
DD
, DV
DD
DV
DDI
(5 V)
DV
DDI
(3 V)
V
INA
V
RT
V
RB
V
RT
– V
RB
V
V
V
V
V
V
V
V
Analog input voltage
Analog reference voltage: T
Analog reference voltage: B
Analog reference voltage range
Digital “H” level
input voltage
CKSEL, CE
OE, DSEL, RESET,
CLKA, CLKB
CLKEP CLKEN
(DV
DDI
= 5 V)
CLKEP CLKEN
(DV
DDI
= 3.3 V)
CKSEL, CE
OE, DSEL, RESET,
CLKA, CLKB
CLKEP CLKEN
(DV
DDI
= 5 V)
CLKEP CLKEN
(DV
DDI
= 3.3 V)
CLKEP CLKEN
(DV
DDI
= 5 V)
CLKEP CLKEN
(DV
DDI
= 3.3 V)
V
IHD
AV
DD
– 0.5
DV
DD
– 0.5
—
—
V
DV
DDI
– 1.1
—
DV
DDI
– 0.6
V
DV
DDI
– 0.5
—
DV
DDI
V
Digital “L” level input
voltage
V
ILD
—
—
0.5
V
—
—
0.5
V
DV
DDI
– 2.0
—
DV
DDI
– 1.45
V
2.3
—
DV
DDI
– 0.5
V
Digital input voltage
range
V
IHD
– V
ILD
0.4
0.8
—
V
0.4
0.6
—
V
Digital input current
Differential clock frequency
Two-phase clock frequency
Minimum clock pulse width (differential)
Minimum clock pulse width (two-phase)
Clock pulse rising/falling time
RESET signal setup time
RESET signal hold time
Operating temperature range
I
ID
–20
0.1
0.1
3.0
6.0
—
1.5
1.5
–20
—
—
—
3.5
7.0
2.0
—
—
—
5
μ
A
MHz
MHz
ns
ns
ns
ns
ns
°
C
f
CLKEP
, f
CLKEN
f
CLKA
, f
CLKB
t
WS+
, t
WS–
t
WD+
, t
WD–
t
r
, t
f
t
s
t
h
Ta
140
70
—
—
—
—
—
70
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB40C318V | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 140 MSPS A/D Converter |
| MB40C318VPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 140 MSPS A/D Converter |
| MB40C328 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
| MB40C328PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
| MB40C328V | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
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