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參數(shù)資料
| 型號： | MB40C318VPFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | ADC |
| 英文描述： | 8-bit 140 MSPS A/D Converter |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | MB40C318VPFV |
9
MB40C318V
I
TIMING DIAGRAM 1
Differential CLK input-straight output mode
CLKEP = CLKEN = 140 MHz (max)
CLKA = CLKB = “L” (DV
SS
)
CKSEL = “H” (AV
DD
)
DSEL = “H” (DV
DD
)
RESET = “H” (DV
DDI
)
CE = “L” (AV
SS
)
OE = “L” (DV
SS
)
Differential CLK input
—
Solid line: CLKEP Dotted line: CLKEN
V
INA
input
—
Sampling at CLKEP rising
(
CLKEN falling
)
D
A0
to D
A7
—
Output (after 5 CLK + t
pdS
from Sampling) at CLKEP rising
(
CLKEN falling
)
V
IHD
V
ILD
V
OHD
V
OLD
D
A0
to
D
A7
V
OHD
V
OLD
D
B0
to
D
B7
V
OHD
V
OLD
CLKOA
V
OHD
V
OLD
CLKOB
DV
DDI
1.1 V
DV
DDI
1.45 V
0.4 V
N
N
+
1
DV
0.4 V
0.4 V
t
AD
t
f
t
r
t
WS
+
t
WS
N
3
N
2
N
1
N
4
N
5
N
6
N
7
N
1
N
+
1
N
+
2
N
+
3
N
+
4
N
+
5
N
+
6
N
+
7
N
t
pdSO
(typ)
t
pdSO
(min)
t
pdSO
(max)
DV
DD
0.4 V
t
pdS
(typ)
t
pdS
(min)
t
pdS
(max)
Differential
CLK input
V
INA
input
ALL “L” fix
ALL “L” fix
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB40C318 | 8-bit 140 MSPS A/D Converter |
| MB40C318PFV | 8-bit 140 MSPS A/D Converter |
| MB40C328V | 8-bit 100 MSPS A/D Converter |
| MB40C328VPFV | 8-bit 100 MSPS A/D Converter |
| MB40C328 | 8-bit 100 MSPS A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB40C328 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
| MB40C328PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
| MB40C328V | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
| MB40C328VPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
| MB40C338 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:3 ch 8-bit 162 MSPS A/D Converter |
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